1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Realtek RTL839X SRAM clock setters
4 * Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
7 #include <asm/mipsregs.h>
8 #include <dt-bindings/clock/rtl83xx-clk.h>
10 #include "clk-rtl83xx.h"
23 .globl rtcl_839x_dram_start
27 * Functions start here and should avoid access to normal memory. REMARK! Do not forget about
28 * stack pointer and dirty caches that might interfere.
31 .globl rtcl_839x_dram_set_rate
32 .ent rtcl_839x_dram_set_rate
33 rtcl_839x_dram_set_rate:
37 /* disable MIPS 34K branch and return prediction */
38 mfc0 rCP0, CP0_CONFIG, 7
40 mtc0 rTMP, CP0_CONFIG, 7
42 li rCTR, RTL_SW_CORE_BASE
43 addiu rGLB, rCTR, RTL839X_PLL_GLB_CTRL
45 beq $a0, rTMP, pre_cpu
47 beq $a0, rTMP, pre_mem
53 addiu rCTR, rCTR, RTL839X_PLL_LXB_CTRL0
55 ori rMSK, $0, RTL839X_GLB_CTRL_LXB_CLKSEL_MASK
57 /* try to avoid memory access with simple 64K data cache flush */
58 li rMSK, RTL_SRAM_BASE
64 bne rTMP, $0, pre_flush
70 addiu rCTR, rCTR, RTL839X_PLL_MEM_CTRL0
72 ori rMSK, $0, RTL839X_GLB_CTRL_MEM_CLKSEL_MASK
77 addiu rCTR, rCTR, RTL839X_PLL_CPU_CTRL0
78 ori rMSK, $0, RTL839X_GLB_CTRL_CPU_CLKSEL_MASK
80 /* switch to fixed clock */
88 /* wait until fixed clock in use */
91 bnez rTMP, wait_fixclock
94 /* set new PLL values */
100 /* wait for value takeover */
106 /* switch back to PLL clock*/
115 /* wait until PLL clock in use */
118 bnez rTMP, wait_pllclock
121 /* restore branch prediction */
122 mtc0 rCP0, CP0_CONFIG, 7
126 #else /* !CONFIG_RTL839X */
133 .end rtcl_839x_dram_set_rate
136 * End marker. Do not delete.
138 .word RTL_SRAM_MARKER
139 .globl rtcl_839x_dram_size
141 .word .-rtcl_839x_dram_start