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ath25: switch default kernel to 5.15
[openwrt/openwrt.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++) {
146 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
147 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
148 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
149 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
150 }
151
152 // Set forwarding action based on inner VLAN tag
153 for (i = 0; i < priv->cpu_port; i++)
154 priv->r->vlan_fwd_on_inner(i, true);
155 }
156
157 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
158 {
159 int i;
160
161 for (i = 0; i < priv->cpu_port; i++)
162 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
163 }
164
165 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
166 int port, bool enable)
167 {
168 int shift = SALRN_PORT_SHIFT(port);
169 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
170
171 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
172 priv->r->l2_port_new_salrn(port));
173 }
174
175 static int rtl83xx_setup(struct dsa_switch *ds)
176 {
177 int i;
178 struct rtl838x_switch_priv *priv = ds->priv;
179
180 pr_debug("%s called\n", __func__);
181
182 /* Disable MAC polling the PHY so that we can start configuration */
183 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
184
185 for (i = 0; i < ds->num_ports; i++)
186 priv->ports[i].enable = false;
187 priv->ports[priv->cpu_port].enable = true;
188
189 /* Configure ports so they are disabled by default, but once enabled
190 * they will work in isolated mode (only traffic between port and CPU).
191 */
192 for (i = 0; i < priv->cpu_port; i++) {
193 if (priv->ports[i].phy) {
194 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
195 priv->r->traffic_set(i, BIT_ULL(i));
196 }
197 }
198 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
199
200 /* For standalone ports, forward packets even if a static fdb
201 * entry for the source address exists on another port.
202 */
203 if (priv->r->set_static_move_action) {
204 for (i = 0; i <= priv->cpu_port; i++)
205 priv->r->set_static_move_action(i, true);
206 }
207
208 if (priv->family_id == RTL8380_FAMILY_ID)
209 rtl838x_print_matrix();
210 else
211 rtl839x_print_matrix();
212
213 rtl83xx_init_stats(priv);
214
215 rtl83xx_vlan_setup(priv);
216
217 rtl83xx_setup_bpdu_traps(priv);
218
219 ds->configure_vlan_while_not_filtering = true;
220
221 priv->r->l2_learning_setup();
222
223 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
224 ds->assisted_learning_on_cpu_port = true;
225
226 /*
227 * Make sure all frames sent to the switch's MAC are trapped to the CPU-port
228 * 0: FWD, 1: DROP, 2: TRAP2CPU
229 */
230 if (priv->family_id == RTL8380_FAMILY_ID)
231 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
232 else
233 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
234
235 /* Enable MAC Polling PHY again */
236 rtl83xx_enable_phy_polling(priv);
237 pr_debug("Please wait until PHY is settled\n");
238 msleep(1000);
239 priv->r->pie_init(priv);
240
241 return 0;
242 }
243
244 static int rtl93xx_setup(struct dsa_switch *ds)
245 {
246 int i;
247 struct rtl838x_switch_priv *priv = ds->priv;
248
249 pr_info("%s called\n", __func__);
250
251 /* Disable MAC polling the PHY so that we can start configuration */
252 if (priv->family_id == RTL9300_FAMILY_ID)
253 sw_w32(0, RTL930X_SMI_POLL_CTRL);
254
255 if (priv->family_id == RTL9310_FAMILY_ID) {
256 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
257 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
258 }
259
260 // Disable all ports except CPU port
261 for (i = 0; i < ds->num_ports; i++)
262 priv->ports[i].enable = false;
263 priv->ports[priv->cpu_port].enable = true;
264
265 /* Configure ports so they are disabled by default, but once enabled
266 * they will work in isolated mode (only traffic between port and CPU).
267 */
268 for (i = 0; i < priv->cpu_port; i++) {
269 if (priv->ports[i].phy) {
270 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
271 priv->r->traffic_set(i, BIT_ULL(i));
272 }
273 }
274 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
275
276 rtl930x_print_matrix();
277
278 // TODO: Initialize statistics
279
280 rtl83xx_vlan_setup(priv);
281
282 ds->configure_vlan_while_not_filtering = true;
283
284 priv->r->l2_learning_setup();
285
286 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
287 ds->assisted_learning_on_cpu_port = true;
288
289 rtl83xx_enable_phy_polling(priv);
290
291 priv->r->pie_init(priv);
292
293 priv->r->led_init(priv);
294
295 return 0;
296 }
297
298 static int rtl93xx_get_sds(struct phy_device *phydev)
299 {
300 struct device *dev = &phydev->mdio.dev;
301 struct device_node *dn;
302 u32 sds_num;
303
304 if (!dev)
305 return -1;
306 if (dev->of_node) {
307 dn = dev->of_node;
308 if (of_property_read_u32(dn, "sds", &sds_num))
309 sds_num = -1;
310 } else {
311 dev_err(dev, "No DT node.\n");
312 return -1;
313 }
314
315 return sds_num;
316 }
317
318 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
319 unsigned long *supported,
320 struct phylink_link_state *state)
321 {
322 struct rtl838x_switch_priv *priv = ds->priv;
323 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
324
325 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
326
327 if (!phy_interface_mode_is_rgmii(state->interface) &&
328 state->interface != PHY_INTERFACE_MODE_NA &&
329 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
330 state->interface != PHY_INTERFACE_MODE_MII &&
331 state->interface != PHY_INTERFACE_MODE_REVMII &&
332 state->interface != PHY_INTERFACE_MODE_GMII &&
333 state->interface != PHY_INTERFACE_MODE_QSGMII &&
334 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
335 state->interface != PHY_INTERFACE_MODE_SGMII) {
336 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
337 dev_err(ds->dev,
338 "Unsupported interface: %d for port %d\n",
339 state->interface, port);
340 return;
341 }
342
343 /* Allow all the expected bits */
344 phylink_set(mask, Autoneg);
345 phylink_set_port_modes(mask);
346 phylink_set(mask, Pause);
347 phylink_set(mask, Asym_Pause);
348
349 /* With the exclusion of MII and Reverse MII, we support Gigabit,
350 * including Half duplex
351 */
352 if (state->interface != PHY_INTERFACE_MODE_MII &&
353 state->interface != PHY_INTERFACE_MODE_REVMII) {
354 phylink_set(mask, 1000baseT_Full);
355 phylink_set(mask, 1000baseT_Half);
356 }
357
358 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
359 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
360 phylink_set(mask, 1000baseX_Full);
361
362 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
363 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
364 phylink_set(mask, 1000baseX_Full);
365
366 phylink_set(mask, 10baseT_Half);
367 phylink_set(mask, 10baseT_Full);
368 phylink_set(mask, 100baseT_Half);
369 phylink_set(mask, 100baseT_Full);
370
371 bitmap_and(supported, supported, mask,
372 __ETHTOOL_LINK_MODE_MASK_NBITS);
373 bitmap_and(state->advertising, state->advertising, mask,
374 __ETHTOOL_LINK_MODE_MASK_NBITS);
375 }
376
377 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
378 unsigned long *supported,
379 struct phylink_link_state *state)
380 {
381 struct rtl838x_switch_priv *priv = ds->priv;
382 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
383
384 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
385 phy_modes(state->interface));
386
387 if (!phy_interface_mode_is_rgmii(state->interface) &&
388 state->interface != PHY_INTERFACE_MODE_NA &&
389 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
390 state->interface != PHY_INTERFACE_MODE_MII &&
391 state->interface != PHY_INTERFACE_MODE_REVMII &&
392 state->interface != PHY_INTERFACE_MODE_GMII &&
393 state->interface != PHY_INTERFACE_MODE_QSGMII &&
394 state->interface != PHY_INTERFACE_MODE_XGMII &&
395 state->interface != PHY_INTERFACE_MODE_HSGMII &&
396 state->interface != PHY_INTERFACE_MODE_10GBASER &&
397 state->interface != PHY_INTERFACE_MODE_10GKR &&
398 state->interface != PHY_INTERFACE_MODE_USXGMII &&
399 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
400 state->interface != PHY_INTERFACE_MODE_SGMII) {
401 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
402 dev_err(ds->dev,
403 "Unsupported interface: %d for port %d\n",
404 state->interface, port);
405 return;
406 }
407
408 /* Allow all the expected bits */
409 phylink_set(mask, Autoneg);
410 phylink_set_port_modes(mask);
411 phylink_set(mask, Pause);
412 phylink_set(mask, Asym_Pause);
413
414 /* With the exclusion of MII and Reverse MII, we support Gigabit,
415 * including Half duplex
416 */
417 if (state->interface != PHY_INTERFACE_MODE_MII &&
418 state->interface != PHY_INTERFACE_MODE_REVMII) {
419 phylink_set(mask, 1000baseT_Full);
420 phylink_set(mask, 1000baseT_Half);
421 }
422
423 // Internal phys of the RTL93xx family provide 10G
424 if (priv->ports[port].phy_is_integrated
425 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
426 phylink_set(mask, 1000baseX_Full);
427 } else if (priv->ports[port].phy_is_integrated) {
428 phylink_set(mask, 1000baseX_Full);
429 phylink_set(mask, 10000baseKR_Full);
430 phylink_set(mask, 10000baseSR_Full);
431 phylink_set(mask, 10000baseCR_Full);
432 }
433 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
434 phylink_set(mask, 1000baseX_Full);
435 phylink_set(mask, 1000baseT_Full);
436 phylink_set(mask, 10000baseKR_Full);
437 phylink_set(mask, 10000baseT_Full);
438 phylink_set(mask, 10000baseSR_Full);
439 phylink_set(mask, 10000baseCR_Full);
440 }
441
442 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
443 phylink_set(mask, 10000baseT_Full);
444
445 phylink_set(mask, 10baseT_Half);
446 phylink_set(mask, 10baseT_Full);
447 phylink_set(mask, 100baseT_Half);
448 phylink_set(mask, 100baseT_Full);
449
450 bitmap_and(supported, supported, mask,
451 __ETHTOOL_LINK_MODE_MASK_NBITS);
452 bitmap_and(state->advertising, state->advertising, mask,
453 __ETHTOOL_LINK_MODE_MASK_NBITS);
454 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
455 }
456
457 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
458 struct phylink_link_state *state)
459 {
460 struct rtl838x_switch_priv *priv = ds->priv;
461 u64 speed;
462 u64 link;
463
464 if (port < 0 || port > priv->cpu_port)
465 return -EINVAL;
466
467 state->link = 0;
468 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
469 if (link & BIT_ULL(port))
470 state->link = 1;
471 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
472
473 state->duplex = 0;
474 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
475 state->duplex = 1;
476
477 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
478 speed >>= (port % 16) << 1;
479 switch (speed & 0x3) {
480 case 0:
481 state->speed = SPEED_10;
482 break;
483 case 1:
484 state->speed = SPEED_100;
485 break;
486 case 2:
487 state->speed = SPEED_1000;
488 break;
489 case 3:
490 if (priv->family_id == RTL9300_FAMILY_ID
491 && (port == 24 || port == 26)) /* Internal serdes */
492 state->speed = SPEED_2500;
493 else
494 state->speed = SPEED_100; /* Is in fact 500Mbit */
495 }
496
497 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
498 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
499 state->pause |= MLO_PAUSE_RX;
500 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
501 state->pause |= MLO_PAUSE_TX;
502 return 1;
503 }
504
505 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
506 struct phylink_link_state *state)
507 {
508 struct rtl838x_switch_priv *priv = ds->priv;
509 u64 speed;
510 u64 link;
511 u64 media;
512
513 if (port < 0 || port > priv->cpu_port)
514 return -EINVAL;
515
516 /*
517 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
518 * state needs to be read twice in order to read a correct result.
519 * This would not be necessary for ports connected e.g. to RTL8218D
520 * PHYs.
521 */
522 state->link = 0;
523 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
524 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
525 if (link & BIT_ULL(port))
526 state->link = 1;
527
528 if (priv->family_id == RTL9310_FAMILY_ID)
529 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
530
531 if (priv->family_id == RTL9300_FAMILY_ID)
532 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
533
534 if (media & BIT_ULL(port))
535 state->link = 1;
536
537 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
538 link & BIT_ULL(port), media);
539
540 state->duplex = 0;
541 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
542 state->duplex = 1;
543
544 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
545 speed >>= (port % 8) << 2;
546 switch (speed & 0xf) {
547 case 0:
548 state->speed = SPEED_10;
549 break;
550 case 1:
551 state->speed = SPEED_100;
552 break;
553 case 2:
554 case 7:
555 state->speed = SPEED_1000;
556 break;
557 case 4:
558 state->speed = SPEED_10000;
559 break;
560 case 5:
561 case 8:
562 state->speed = SPEED_2500;
563 break;
564 case 6:
565 state->speed = SPEED_5000;
566 break;
567 default:
568 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
569 }
570
571 if (priv->family_id == RTL9310_FAMILY_ID
572 && (port >= 52 || port <= 55)) { /* Internal serdes */
573 state->speed = SPEED_10000;
574 state->link = 1;
575 state->duplex = 1;
576 }
577
578 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
579 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
580 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
581 state->pause |= MLO_PAUSE_RX;
582 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
583 state->pause |= MLO_PAUSE_TX;
584 return 1;
585 }
586
587 static void rtl83xx_config_interface(int port, phy_interface_t interface)
588 {
589 u32 old, int_shift, sds_shift;
590
591 switch (port) {
592 case 24:
593 int_shift = 0;
594 sds_shift = 5;
595 break;
596 case 26:
597 int_shift = 3;
598 sds_shift = 0;
599 break;
600 default:
601 return;
602 }
603
604 old = sw_r32(RTL838X_SDS_MODE_SEL);
605 switch (interface) {
606 case PHY_INTERFACE_MODE_1000BASEX:
607 if ((old >> sds_shift & 0x1f) == 4)
608 return;
609 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
610 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
611 break;
612 case PHY_INTERFACE_MODE_SGMII:
613 if ((old >> sds_shift & 0x1f) == 2)
614 return;
615 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
616 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
617 break;
618 default:
619 return;
620 }
621 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
622 }
623
624 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
625 unsigned int mode,
626 const struct phylink_link_state *state)
627 {
628 struct rtl838x_switch_priv *priv = ds->priv;
629 u32 reg;
630 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
631
632 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
633
634 if (port == priv->cpu_port) {
635 /* Set Speed, duplex, flow control
636 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
637 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
638 * | MEDIA_SEL
639 */
640 if (priv->family_id == RTL8380_FAMILY_ID) {
641 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
642 /* allow CRC errors on CPU-port */
643 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
644 } else {
645 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
646 }
647 return;
648 }
649
650 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
651 /* Auto-Negotiation does not work for MAC in RTL8390 */
652 if (priv->family_id == RTL8380_FAMILY_ID) {
653 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
654 pr_debug("PHY autonegotiates\n");
655 reg |= RTL838X_NWAY_EN;
656 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
657 rtl83xx_config_interface(port, state->interface);
658 return;
659 }
660 }
661
662 if (mode != MLO_AN_FIXED)
663 pr_debug("Fixed state.\n");
664
665 /* Clear id_mode_dis bit, and the existing port mode, let
666 * RGMII_MODE_EN bet set by mac_link_{up,down} */
667 if (priv->family_id == RTL8380_FAMILY_ID) {
668 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
669 if (state->pause & MLO_PAUSE_TXRX_MASK) {
670 if (state->pause & MLO_PAUSE_TX)
671 reg |= RTL838X_TX_PAUSE_EN;
672 reg |= RTL838X_RX_PAUSE_EN;
673 }
674 } else if (priv->family_id == RTL8390_FAMILY_ID) {
675 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
676 if (state->pause & MLO_PAUSE_TXRX_MASK) {
677 if (state->pause & MLO_PAUSE_TX)
678 reg |= RTL839X_TX_PAUSE_EN;
679 reg |= RTL839X_RX_PAUSE_EN;
680 }
681 }
682
683
684 reg &= ~(3 << speed_bit);
685 switch (state->speed) {
686 case SPEED_1000:
687 reg |= 2 << speed_bit;
688 break;
689 case SPEED_100:
690 reg |= 1 << speed_bit;
691 break;
692 default:
693 break; // Ignore, including 10MBit which has a speed value of 0
694 }
695
696 if (priv->family_id == RTL8380_FAMILY_ID) {
697 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
698 if (state->link)
699 reg |= RTL838X_FORCE_LINK_EN;
700 if (state->duplex == RTL838X_DUPLEX_MODE)
701 reg |= RTL838X_DUPLEX_MODE;
702 } else if (priv->family_id == RTL8390_FAMILY_ID) {
703 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
704 if (state->link)
705 reg |= RTL839X_FORCE_LINK_EN;
706 if (state->duplex == RTL839X_DUPLEX_MODE)
707 reg |= RTL839X_DUPLEX_MODE;
708 }
709
710 // LAG members must use DUPLEX and we need to enable the link
711 if (priv->lagmembers & BIT_ULL(port)) {
712 switch(priv->family_id) {
713 case RTL8380_FAMILY_ID:
714 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
715 break;
716 case RTL8390_FAMILY_ID:
717 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
718 break;
719 }
720 }
721
722 // Disable AN
723 if (priv->family_id == RTL8380_FAMILY_ID)
724 reg &= ~RTL838X_NWAY_EN;
725 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
726 }
727
728 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
729 unsigned int mode,
730 const struct phylink_link_state *state)
731 {
732 struct rtl838x_switch_priv *priv = ds->priv;
733 int sds_num;
734 u32 reg, band;
735
736 sds_num = priv->ports[port].sds_num;
737 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
738
739 switch (state->interface) {
740 case PHY_INTERFACE_MODE_HSGMII:
741 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
742 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
743 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
744 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
745 break;
746 case PHY_INTERFACE_MODE_1000BASEX:
747 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
748 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
749 break;
750 case PHY_INTERFACE_MODE_XGMII:
751 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
752 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
753 break;
754 case PHY_INTERFACE_MODE_10GBASER:
755 case PHY_INTERFACE_MODE_10GKR:
756 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
757 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
758 break;
759 case PHY_INTERFACE_MODE_USXGMII:
760 // Translates to MII_USXGMII_10GSXGMII
761 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
762 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
763 break;
764 case PHY_INTERFACE_MODE_SGMII:
765 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
766 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
767 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
768 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
769 break;
770 case PHY_INTERFACE_MODE_QSGMII:
771 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
772 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
773 break;
774 default:
775 pr_err("%s: unknown serdes mode: %s\n",
776 __func__, phy_modes(state->interface));
777 return;
778 }
779
780 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
781 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
782
783 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
784
785 reg &= ~(0xf << 12);
786 reg |= 0x2 << 12; // Set SMI speed to 0x2
787
788 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
789
790 if (priv->lagmembers & BIT_ULL(port))
791 reg |= RTL931X_DUPLEX_MODE;
792
793 if (state->duplex == DUPLEX_FULL)
794 reg |= RTL931X_DUPLEX_MODE;
795
796 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
797
798 }
799
800 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
801 unsigned int mode,
802 const struct phylink_link_state *state)
803 {
804 struct rtl838x_switch_priv *priv = ds->priv;
805 int sds_num, sds_mode;
806 u32 reg;
807
808 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
809 port, mode, phy_modes(state->interface), state->speed, state->link);
810
811 // Nothing to be done for the CPU-port
812 if (port == priv->cpu_port)
813 return;
814
815 if (priv->family_id == RTL9310_FAMILY_ID)
816 return rtl931x_phylink_mac_config(ds, port, mode, state);
817
818 sds_num = priv->ports[port].sds_num;
819 pr_info("%s SDS is %d\n", __func__, sds_num);
820 if (sds_num >= 0) {
821 switch (state->interface) {
822 case PHY_INTERFACE_MODE_HSGMII:
823 sds_mode = 0x12;
824 break;
825 case PHY_INTERFACE_MODE_1000BASEX:
826 sds_mode = 0x04;
827 break;
828 case PHY_INTERFACE_MODE_XGMII:
829 sds_mode = 0x10;
830 break;
831 case PHY_INTERFACE_MODE_10GBASER:
832 case PHY_INTERFACE_MODE_10GKR:
833 sds_mode = 0x1b; // 10G 1000X Auto
834 break;
835 case PHY_INTERFACE_MODE_USXGMII:
836 sds_mode = 0x0d;
837 break;
838 default:
839 pr_err("%s: unknown serdes mode: %s\n",
840 __func__, phy_modes(state->interface));
841 return;
842 }
843 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
844 rtl9300_serdes_setup(sds_num, state->interface);
845 }
846
847 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
848 reg &= ~(0xf << 3);
849
850 switch (state->speed) {
851 case SPEED_10000:
852 reg |= 4 << 3;
853 break;
854 case SPEED_5000:
855 reg |= 6 << 3;
856 break;
857 case SPEED_2500:
858 reg |= 5 << 3;
859 break;
860 case SPEED_1000:
861 reg |= 2 << 3;
862 break;
863 default:
864 reg |= 2 << 3;
865 break;
866 }
867
868 if (state->link)
869 reg |= RTL930X_FORCE_LINK_EN;
870
871 if (priv->lagmembers & BIT_ULL(port))
872 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
873
874 if (state->duplex == DUPLEX_FULL)
875 reg |= RTL930X_DUPLEX_MODE;
876
877 if (priv->ports[port].phy_is_integrated)
878 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
879 else
880 reg |= RTL930X_FORCE_EN;
881
882 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
883 }
884
885 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
886 unsigned int mode,
887 phy_interface_t interface)
888 {
889 struct rtl838x_switch_priv *priv = ds->priv;
890
891 /* Stop TX/RX to port */
892 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
893
894 // No longer force link
895 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
896 }
897
898 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
899 unsigned int mode,
900 phy_interface_t interface)
901 {
902 struct rtl838x_switch_priv *priv = ds->priv;
903 u32 v = 0;
904
905 /* Stop TX/RX to port */
906 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
907
908 // No longer force link
909 if (priv->family_id == RTL9300_FAMILY_ID)
910 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
911 else if (priv->family_id == RTL9310_FAMILY_ID)
912 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
913 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
914 }
915
916 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
917 unsigned int mode,
918 phy_interface_t interface,
919 struct phy_device *phydev,
920 int speed, int duplex,
921 bool tx_pause, bool rx_pause)
922 {
923 struct rtl838x_switch_priv *priv = ds->priv;
924 /* Restart TX/RX to port */
925 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
926 // TODO: Set speed/duplex/pauses
927 }
928
929 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
930 unsigned int mode,
931 phy_interface_t interface,
932 struct phy_device *phydev,
933 int speed, int duplex,
934 bool tx_pause, bool rx_pause)
935 {
936 struct rtl838x_switch_priv *priv = ds->priv;
937
938 /* Restart TX/RX to port */
939 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
940 // TODO: Set speed/duplex/pauses
941 }
942
943 static void rtl83xx_get_strings(struct dsa_switch *ds,
944 int port, u32 stringset, u8 *data)
945 {
946 int i;
947
948 if (stringset != ETH_SS_STATS)
949 return;
950
951 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
952 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
953 ETH_GSTRING_LEN);
954 }
955
956 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
957 uint64_t *data)
958 {
959 struct rtl838x_switch_priv *priv = ds->priv;
960 const struct rtl83xx_mib_desc *mib;
961 int i;
962 u64 h;
963
964 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
965 mib = &rtl83xx_mib[i];
966
967 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
968 if (mib->size == 2) {
969 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
970 data[i] |= h << 32;
971 }
972 }
973 }
974
975 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
976 {
977 if (sset != ETH_SS_STATS)
978 return 0;
979
980 return ARRAY_SIZE(rtl83xx_mib);
981 }
982
983 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
984 {
985 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
986 u64 portmask;
987
988 if (mc_group >= MAX_MC_GROUPS - 1)
989 return -1;
990
991 set_bit(mc_group, priv->mc_group_bm);
992 portmask = BIT_ULL(port);
993 priv->r->write_mcast_pmask(mc_group, portmask);
994
995 return mc_group;
996 }
997
998 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
999 {
1000 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1001
1002 pr_debug("%s: %d\n", __func__, port);
1003
1004 portmask |= BIT_ULL(port);
1005 priv->r->write_mcast_pmask(mc_group, portmask);
1006
1007 return portmask;
1008 }
1009
1010 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1011 {
1012 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1013
1014 pr_debug("%s: %d\n", __func__, port);
1015
1016 portmask &= ~BIT_ULL(port);
1017 priv->r->write_mcast_pmask(mc_group, portmask);
1018 if (!portmask)
1019 clear_bit(mc_group, priv->mc_group_bm);
1020
1021 return portmask;
1022 }
1023
1024 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1025 struct phy_device *phydev)
1026 {
1027 struct rtl838x_switch_priv *priv = ds->priv;
1028 u64 v;
1029
1030 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1031 priv->ports[port].enable = true;
1032
1033 /* enable inner tagging on egress, do not keep any tags */
1034 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1035
1036 if (dsa_is_cpu_port(ds, port))
1037 return 0;
1038
1039 /* add port to switch mask of CPU_PORT */
1040 priv->r->traffic_enable(priv->cpu_port, port);
1041
1042 if (priv->is_lagmember[port]) {
1043 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1044 return 0;
1045 }
1046
1047 /* add all other ports in the same bridge to switch mask of port */
1048 v = priv->r->traffic_get(port);
1049 v |= priv->ports[port].pm;
1050 priv->r->traffic_set(port, v);
1051
1052 // TODO: Figure out if this is necessary
1053 if (priv->family_id == RTL9300_FAMILY_ID) {
1054 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1055 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1056 }
1057
1058 if (priv->ports[port].sds_num < 0)
1059 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1060
1061 return 0;
1062 }
1063
1064 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1065 {
1066 struct rtl838x_switch_priv *priv = ds->priv;
1067 u64 v;
1068
1069 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1070 /* you can only disable user ports */
1071 if (!dsa_is_user_port(ds, port))
1072 return;
1073
1074 // BUG: This does not work on RTL931X
1075 /* remove port from switch mask of CPU_PORT */
1076 priv->r->traffic_disable(priv->cpu_port, port);
1077
1078 /* remove all other ports in the same bridge from switch mask of port */
1079 v = priv->r->traffic_get(port);
1080 v &= ~priv->ports[port].pm;
1081 priv->r->traffic_set(port, v);
1082
1083 priv->ports[port].enable = false;
1084 }
1085
1086 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1087 struct ethtool_eee *e)
1088 {
1089 struct rtl838x_switch_priv *priv = ds->priv;
1090
1091 if (e->eee_enabled && !priv->eee_enabled) {
1092 pr_info("Globally enabling EEE\n");
1093 priv->r->init_eee(priv, true);
1094 }
1095
1096 priv->r->port_eee_set(priv, port, e->eee_enabled);
1097
1098 if (e->eee_enabled)
1099 pr_info("Enabled EEE for port %d\n", port);
1100 else
1101 pr_info("Disabled EEE for port %d\n", port);
1102 return 0;
1103 }
1104
1105 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1106 struct ethtool_eee *e)
1107 {
1108 struct rtl838x_switch_priv *priv = ds->priv;
1109
1110 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1111
1112 priv->r->eee_port_ability(priv, e, port);
1113
1114 e->eee_enabled = priv->ports[port].eee_enabled;
1115
1116 e->eee_active = !!(e->advertised & e->lp_advertised);
1117
1118 return 0;
1119 }
1120
1121 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1122 struct ethtool_eee *e)
1123 {
1124 struct rtl838x_switch_priv *priv = ds->priv;
1125
1126 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
1127 | SUPPORTED_2500baseX_Full;
1128
1129 priv->r->eee_port_ability(priv, e, port);
1130
1131 e->eee_enabled = priv->ports[port].eee_enabled;
1132
1133 e->eee_active = !!(e->advertised & e->lp_advertised);
1134
1135 return 0;
1136 }
1137
1138 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1139 {
1140 struct rtl838x_switch_priv *priv = ds->priv;
1141
1142 priv->r->set_ageing_time(msec);
1143 return 0;
1144 }
1145
1146 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1147 struct net_device *bridge)
1148 {
1149 struct rtl838x_switch_priv *priv = ds->priv;
1150 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1151 int i;
1152
1153 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1154
1155 if (priv->is_lagmember[port]) {
1156 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1157 return 0;
1158 }
1159
1160 mutex_lock(&priv->reg_mutex);
1161 for (i = 0; i < ds->num_ports; i++) {
1162 /* Add this port to the port matrix of the other ports in the
1163 * same bridge. If the port is disabled, port matrix is kept
1164 * and not being setup until the port becomes enabled.
1165 */
1166 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1167 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1168 continue;
1169 if (priv->ports[i].enable)
1170 priv->r->traffic_enable(i, port);
1171
1172 priv->ports[i].pm |= BIT_ULL(port);
1173 port_bitmap |= BIT_ULL(i);
1174 }
1175 }
1176
1177 /* Add all other ports to this port matrix. */
1178 if (priv->ports[port].enable) {
1179 priv->r->traffic_enable(priv->cpu_port, port);
1180 v = priv->r->traffic_get(port);
1181 v |= port_bitmap;
1182 priv->r->traffic_set(port, v);
1183 }
1184 priv->ports[port].pm |= port_bitmap;
1185
1186 if (priv->r->set_static_move_action)
1187 priv->r->set_static_move_action(port, false);
1188
1189 mutex_unlock(&priv->reg_mutex);
1190
1191 return 0;
1192 }
1193
1194 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1195 struct net_device *bridge)
1196 {
1197 struct rtl838x_switch_priv *priv = ds->priv;
1198 u64 port_bitmap = 0, v;
1199 int i;
1200
1201 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1202 mutex_lock(&priv->reg_mutex);
1203 for (i = 0; i < ds->num_ports; i++) {
1204 /* Remove this port from the port matrix of the other ports
1205 * in the same bridge. If the port is disabled, port matrix
1206 * is kept and not being setup until the port becomes enabled.
1207 * And the other port's port matrix cannot be broken when the
1208 * other port is still a VLAN-aware port.
1209 */
1210 if (dsa_is_user_port(ds, i) && i != port) {
1211 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1212 continue;
1213 if (priv->ports[i].enable)
1214 priv->r->traffic_disable(i, port);
1215
1216 priv->ports[i].pm &= ~BIT_ULL(port);
1217 port_bitmap |= BIT_ULL(i);
1218 }
1219 }
1220
1221 /* Remove all other ports from this port matrix. */
1222 if (priv->ports[port].enable) {
1223 v = priv->r->traffic_get(port);
1224 v &= ~port_bitmap;
1225 priv->r->traffic_set(port, v);
1226 }
1227 priv->ports[port].pm &= ~port_bitmap;
1228
1229 if (priv->r->set_static_move_action)
1230 priv->r->set_static_move_action(port, true);
1231
1232 mutex_unlock(&priv->reg_mutex);
1233 }
1234
1235 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1236 {
1237 u32 msti = 0;
1238 u32 port_state[4];
1239 int index, bit;
1240 int pos = port;
1241 struct rtl838x_switch_priv *priv = ds->priv;
1242 int n = priv->port_width << 1;
1243
1244 /* Ports above or equal CPU port can never be configured */
1245 if (port >= priv->cpu_port)
1246 return;
1247
1248 mutex_lock(&priv->reg_mutex);
1249
1250 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1251 * have 64 bit fields, 839x and 931x have 128 bit fields
1252 */
1253 if (priv->family_id == RTL8390_FAMILY_ID)
1254 pos += 12;
1255 if (priv->family_id == RTL9300_FAMILY_ID)
1256 pos += 3;
1257 if (priv->family_id == RTL9310_FAMILY_ID)
1258 pos += 8;
1259
1260 index = n - (pos >> 4) - 1;
1261 bit = (pos << 1) % 32;
1262
1263 priv->r->stp_get(priv, msti, port_state);
1264
1265 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1266 port_state[index] &= ~(3 << bit);
1267
1268 switch (state) {
1269 case BR_STATE_DISABLED: /* 0 */
1270 port_state[index] |= (0 << bit);
1271 break;
1272 case BR_STATE_BLOCKING: /* 4 */
1273 case BR_STATE_LISTENING: /* 1 */
1274 port_state[index] |= (1 << bit);
1275 break;
1276 case BR_STATE_LEARNING: /* 2 */
1277 port_state[index] |= (2 << bit);
1278 break;
1279 case BR_STATE_FORWARDING: /* 3*/
1280 port_state[index] |= (3 << bit);
1281 default:
1282 break;
1283 }
1284
1285 priv->r->stp_set(priv, msti, port_state);
1286
1287 mutex_unlock(&priv->reg_mutex);
1288 }
1289
1290 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1291 {
1292 struct rtl838x_switch_priv *priv = ds->priv;
1293 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1294
1295 pr_debug("FAST AGE port %d\n", port);
1296 mutex_lock(&priv->reg_mutex);
1297 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1298 * port fields:
1299 * 0-4: Replacing port
1300 * 5-9: Flushed/replaced port
1301 * 10-21: FVID
1302 * 22: Entry types: 1: dynamic, 0: also static
1303 * 23: Match flush port
1304 * 24: Match FVID
1305 * 25: Flush (0) or replace (1) L2 entries
1306 * 26: Status of action (1: Start, 0: Done)
1307 */
1308 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1309
1310 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1311
1312 mutex_unlock(&priv->reg_mutex);
1313 }
1314
1315 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1316 {
1317 struct rtl838x_switch_priv *priv = ds->priv;
1318
1319 pr_info("%s port %d\n", __func__, port);
1320 mutex_lock(&priv->reg_mutex);
1321 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1322
1323 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1324
1325 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1326
1327 mutex_unlock(&priv->reg_mutex);
1328 }
1329
1330 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1331 {
1332 struct rtl838x_switch_priv *priv = ds->priv;
1333
1334 if (priv->family_id == RTL9310_FAMILY_ID)
1335 return rtl931x_fast_age(ds, port);
1336
1337 pr_debug("FAST AGE port %d\n", port);
1338 mutex_lock(&priv->reg_mutex);
1339 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1340
1341 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1342
1343 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1344
1345 mutex_unlock(&priv->reg_mutex);
1346 }
1347
1348 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1349 bool vlan_filtering,
1350 struct switchdev_trans *trans)
1351 {
1352 struct rtl838x_switch_priv *priv = ds->priv;
1353
1354 pr_debug("%s: port %d\n", __func__, port);
1355 mutex_lock(&priv->reg_mutex);
1356
1357 if (vlan_filtering) {
1358 /* Enable ingress and egress filtering
1359 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1360 * the filter action:
1361 * 0: Always Forward
1362 * 1: Drop packet
1363 * 2: Trap packet to CPU port
1364 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1365 */
1366 if (port != priv->cpu_port)
1367 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1368
1369 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1370 } else {
1371 /* Disable ingress and egress filtering */
1372 if (port != priv->cpu_port)
1373 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1374
1375 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1376 }
1377
1378 /* Do we need to do something to the CPU-Port, too? */
1379 mutex_unlock(&priv->reg_mutex);
1380
1381 return 0;
1382 }
1383
1384 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1385 const struct switchdev_obj_port_vlan *vlan)
1386 {
1387 struct rtl838x_vlan_info info;
1388 struct rtl838x_switch_priv *priv = ds->priv;
1389
1390 priv->r->vlan_tables_read(0, &info);
1391
1392 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1393 info.tagged_ports, info.untagged_ports, info.profile_id,
1394 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1395
1396 priv->r->vlan_tables_read(1, &info);
1397 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1398 info.tagged_ports, info.untagged_ports, info.profile_id,
1399 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1400 priv->r->vlan_set_untagged(1, info.untagged_ports);
1401 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1402
1403 priv->r->vlan_set_tagged(1, &info);
1404 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1405
1406 return 0;
1407 }
1408
1409 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1410 int port, int pvid)
1411 {
1412 /* Set both inner and outer PVID of the port */
1413 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1414 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1415 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1416 PBVLAN_MODE_UNTAG_AND_PRITAG);
1417 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1418 PBVLAN_MODE_UNTAG_AND_PRITAG);
1419
1420 priv->ports[port].pvid = pvid;
1421 }
1422
1423 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1424 const struct switchdev_obj_port_vlan *vlan)
1425 {
1426 struct rtl838x_vlan_info info;
1427 struct rtl838x_switch_priv *priv = ds->priv;
1428 int v;
1429
1430 pr_debug("%s port %d, vid_begin %d, vid_end %d, flags %x\n", __func__,
1431 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1432
1433 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1434 dev_err(priv->dev, "VLAN out of range: %d - %d",
1435 vlan->vid_begin, vlan->vid_end);
1436 return;
1437 }
1438
1439 mutex_lock(&priv->reg_mutex);
1440
1441 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1442 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1443 rtl83xx_vlan_set_pvid(priv, port, v);
1444 else if (priv->ports[port].pvid == v)
1445 rtl83xx_vlan_set_pvid(priv, port, 0);
1446 }
1447
1448 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1449 /* Get port memberships of this vlan */
1450 priv->r->vlan_tables_read(v, &info);
1451
1452 /* new VLAN? */
1453 if (!info.tagged_ports) {
1454 info.fid = 0;
1455 info.hash_mc_fid = false;
1456 info.hash_uc_fid = false;
1457 info.profile_id = 0;
1458 }
1459
1460 /* sanitize untagged_ports - must be a subset */
1461 if (info.untagged_ports & ~info.tagged_ports)
1462 info.untagged_ports = 0;
1463
1464 info.tagged_ports |= BIT_ULL(port);
1465 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1466 info.untagged_ports |= BIT_ULL(port);
1467 else
1468 info.untagged_ports &= ~BIT_ULL(port);
1469
1470 priv->r->vlan_set_untagged(v, info.untagged_ports);
1471 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1472
1473 priv->r->vlan_set_tagged(v, &info);
1474 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1475 }
1476
1477 mutex_unlock(&priv->reg_mutex);
1478 }
1479
1480 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1481 const struct switchdev_obj_port_vlan *vlan)
1482 {
1483 struct rtl838x_vlan_info info;
1484 struct rtl838x_switch_priv *priv = ds->priv;
1485 int v;
1486 u16 pvid;
1487
1488 pr_debug("%s: port %d, vid_begin %d, vid_end %d, flags %x\n", __func__,
1489 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1490
1491 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1492 dev_err(priv->dev, "VLAN out of range: %d - %d",
1493 vlan->vid_begin, vlan->vid_end);
1494 return -ENOTSUPP;
1495 }
1496
1497 mutex_lock(&priv->reg_mutex);
1498 pvid = priv->ports[port].pvid;
1499
1500 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1501 /* Reset to default if removing the current PVID */
1502 if (v == pvid) {
1503 rtl83xx_vlan_set_pvid(priv, port, 0);
1504 }
1505 /* Get port memberships of this vlan */
1506 priv->r->vlan_tables_read(v, &info);
1507
1508 /* remove port from both tables */
1509 info.untagged_ports &= (~BIT_ULL(port));
1510 info.tagged_ports &= (~BIT_ULL(port));
1511
1512 priv->r->vlan_set_untagged(v, info.untagged_ports);
1513 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1514
1515 priv->r->vlan_set_tagged(v, &info);
1516 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1517 }
1518 mutex_unlock(&priv->reg_mutex);
1519
1520 return 0;
1521 }
1522
1523 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1524 {
1525 memset(e, 0, sizeof(*e));
1526
1527 e->type = L2_UNICAST;
1528 e->valid = true;
1529
1530 e->age = 3;
1531 e->is_static = true;
1532
1533 e->port = port;
1534
1535 e->rvid = e->vid = vid;
1536 e->is_ip_mc = e->is_ipv6_mc = false;
1537 u64_to_ether_addr(mac, e->mac);
1538 }
1539
1540 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1541 {
1542 memset(e, 0, sizeof(*e));
1543
1544 e->type = L2_MULTICAST;
1545 e->valid = true;
1546
1547 e->mc_portmask_index = mc_group;
1548
1549 e->rvid = e->vid = vid;
1550 e->is_ip_mc = e->is_ipv6_mc = false;
1551 u64_to_ether_addr(mac, e->mac);
1552 }
1553
1554 /*
1555 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1556 * over the entries in the bucket until either a matching entry is found or an empty slot
1557 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1558 * when an empty slot was found and must exist is false, the index of the slot is returned
1559 * when no slots are available returns -1
1560 */
1561 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1562 bool must_exist, struct rtl838x_l2_entry *e)
1563 {
1564 int i, idx = -1;
1565 u32 key = priv->r->l2_hash_key(priv, seed);
1566 u64 entry;
1567
1568 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1569 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1570 for (i = 0; i < priv->l2_bucket_size; i++) {
1571 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1572 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1573 if (must_exist && !e->valid)
1574 continue;
1575 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1576 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1577 break;
1578 }
1579 }
1580
1581 return idx;
1582 }
1583
1584 /*
1585 * Uses the seed to identify an entry in the CAM by looping over all its entries
1586 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1587 * when an empty slot was found the index of the slot is returned
1588 * when no slots are available returns -1
1589 */
1590 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1591 bool must_exist, struct rtl838x_l2_entry *e)
1592 {
1593 int i, idx = -1;
1594 u64 entry;
1595
1596 for (i = 0; i < 64; i++) {
1597 entry = priv->r->read_cam(i, e);
1598 if (!must_exist && !e->valid) {
1599 if (idx < 0) /* First empty entry? */
1600 idx = i;
1601 break;
1602 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1603 pr_debug("Found entry in CAM\n");
1604 idx = i;
1605 break;
1606 }
1607 }
1608 return idx;
1609 }
1610
1611 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1612 const unsigned char *addr, u16 vid)
1613 {
1614 struct rtl838x_switch_priv *priv = ds->priv;
1615 u64 mac = ether_addr_to_u64(addr);
1616 struct rtl838x_l2_entry e;
1617 int err = 0, idx;
1618 u64 seed = priv->r->l2_hash_seed(mac, vid);
1619
1620 if (priv->is_lagmember[port]) {
1621 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1622 return 0;
1623 }
1624
1625 mutex_lock(&priv->reg_mutex);
1626
1627 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1628
1629 // Found an existing or empty entry
1630 if (idx >= 0) {
1631 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1632 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1633 goto out;
1634 }
1635
1636 // Hash buckets full, try CAM
1637 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1638
1639 if (idx >= 0) {
1640 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1641 priv->r->write_cam(idx, &e);
1642 goto out;
1643 }
1644
1645 err = -ENOTSUPP;
1646 out:
1647 mutex_unlock(&priv->reg_mutex);
1648 return err;
1649 }
1650
1651 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1652 const unsigned char *addr, u16 vid)
1653 {
1654 struct rtl838x_switch_priv *priv = ds->priv;
1655 u64 mac = ether_addr_to_u64(addr);
1656 struct rtl838x_l2_entry e;
1657 int err = 0, idx;
1658 u64 seed = priv->r->l2_hash_seed(mac, vid);
1659
1660 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1661 mutex_lock(&priv->reg_mutex);
1662
1663 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1664
1665 if (idx >= 0) {
1666 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1667 e.valid = false;
1668 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1669 goto out;
1670 }
1671
1672 /* Check CAM for spillover from hash buckets */
1673 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1674
1675 if (idx >= 0) {
1676 e.valid = false;
1677 priv->r->write_cam(idx, &e);
1678 goto out;
1679 }
1680 err = -ENOENT;
1681 out:
1682 mutex_unlock(&priv->reg_mutex);
1683 return err;
1684 }
1685
1686 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1687 dsa_fdb_dump_cb_t *cb, void *data)
1688 {
1689 struct rtl838x_l2_entry e;
1690 struct rtl838x_switch_priv *priv = ds->priv;
1691 int i;
1692
1693 mutex_lock(&priv->reg_mutex);
1694
1695 for (i = 0; i < priv->fib_entries; i++) {
1696 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1697
1698 if (!e.valid)
1699 continue;
1700
1701 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1702 cb(e.mac, e.vid, e.is_static, data);
1703
1704 if (!((i + 1) % 64))
1705 cond_resched();
1706 }
1707
1708 for (i = 0; i < 64; i++) {
1709 priv->r->read_cam(i, &e);
1710
1711 if (!e.valid)
1712 continue;
1713
1714 if (e.port == port)
1715 cb(e.mac, e.vid, e.is_static, data);
1716 }
1717
1718 mutex_unlock(&priv->reg_mutex);
1719 return 0;
1720 }
1721
1722 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1723 const struct switchdev_obj_port_mdb *mdb)
1724 {
1725 struct rtl838x_switch_priv *priv = ds->priv;
1726
1727 if (priv->id >= 0x9300)
1728 return -EOPNOTSUPP;
1729
1730 return 0;
1731 }
1732
1733 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1734 const struct switchdev_obj_port_mdb *mdb)
1735 {
1736 struct rtl838x_switch_priv *priv = ds->priv;
1737 u64 mac = ether_addr_to_u64(mdb->addr);
1738 struct rtl838x_l2_entry e;
1739 int err = 0, idx;
1740 int vid = mdb->vid;
1741 u64 seed = priv->r->l2_hash_seed(mac, vid);
1742 int mc_group;
1743
1744 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1745
1746 if (priv->is_lagmember[port]) {
1747 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1748 return;
1749 }
1750
1751 mutex_lock(&priv->reg_mutex);
1752
1753 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1754
1755 // Found an existing or empty entry
1756 if (idx >= 0) {
1757 if (e.valid) {
1758 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1759 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1760 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1761 } else {
1762 pr_debug("New entry for seed %016llx\n", seed);
1763 mc_group = rtl83xx_mc_group_alloc(priv, port);
1764 if (mc_group < 0) {
1765 err = -ENOTSUPP;
1766 goto out;
1767 }
1768 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1769 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1770 }
1771 goto out;
1772 }
1773
1774 // Hash buckets full, try CAM
1775 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1776
1777 if (idx >= 0) {
1778 if (e.valid) {
1779 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1780 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1781 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1782 } else {
1783 pr_debug("New entry\n");
1784 mc_group = rtl83xx_mc_group_alloc(priv, port);
1785 if (mc_group < 0) {
1786 err = -ENOTSUPP;
1787 goto out;
1788 }
1789 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1790 priv->r->write_cam(idx, &e);
1791 }
1792 goto out;
1793 }
1794
1795 err = -ENOTSUPP;
1796 out:
1797 mutex_unlock(&priv->reg_mutex);
1798 if (err)
1799 dev_err(ds->dev, "failed to add MDB entry\n");
1800 }
1801
1802 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1803 const struct switchdev_obj_port_mdb *mdb)
1804 {
1805 struct rtl838x_switch_priv *priv = ds->priv;
1806 u64 mac = ether_addr_to_u64(mdb->addr);
1807 struct rtl838x_l2_entry e;
1808 int err = 0, idx;
1809 int vid = mdb->vid;
1810 u64 seed = priv->r->l2_hash_seed(mac, vid);
1811 u64 portmask;
1812
1813 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1814
1815 if (priv->is_lagmember[port]) {
1816 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1817 return 0;
1818 }
1819
1820 mutex_lock(&priv->reg_mutex);
1821
1822 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1823
1824 if (idx >= 0) {
1825 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1826 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1827 if (!portmask) {
1828 e.valid = false;
1829 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1830 }
1831 goto out;
1832 }
1833
1834 /* Check CAM for spillover from hash buckets */
1835 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1836
1837 if (idx >= 0) {
1838 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1839 if (!portmask) {
1840 e.valid = false;
1841 priv->r->write_cam(idx, &e);
1842 }
1843 goto out;
1844 }
1845 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1846 out:
1847 mutex_unlock(&priv->reg_mutex);
1848 return err;
1849 }
1850
1851 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1852 struct dsa_mall_mirror_tc_entry *mirror,
1853 bool ingress)
1854 {
1855 /* We support 4 mirror groups, one destination port per group */
1856 int group;
1857 struct rtl838x_switch_priv *priv = ds->priv;
1858 int ctrl_reg, dpm_reg, spm_reg;
1859
1860 pr_debug("In %s\n", __func__);
1861
1862 for (group = 0; group < 4; group++) {
1863 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1864 break;
1865 }
1866 if (group >= 4) {
1867 for (group = 0; group < 4; group++) {
1868 if (priv->mirror_group_ports[group] < 0)
1869 break;
1870 }
1871 }
1872
1873 if (group >= 4)
1874 return -ENOSPC;
1875
1876 ctrl_reg = priv->r->mir_ctrl + group * 4;
1877 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1878 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1879
1880 pr_debug("Using group %d\n", group);
1881 mutex_lock(&priv->reg_mutex);
1882
1883 if (priv->family_id == RTL8380_FAMILY_ID) {
1884 /* Enable mirroring to port across VLANs (bit 11) */
1885 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1886 } else {
1887 /* Enable mirroring to destination port */
1888 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1889 }
1890
1891 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1892 mutex_unlock(&priv->reg_mutex);
1893 return -EEXIST;
1894 }
1895 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1896 mutex_unlock(&priv->reg_mutex);
1897 return -EEXIST;
1898 }
1899
1900 if (ingress)
1901 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1902 else
1903 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1904
1905 priv->mirror_group_ports[group] = mirror->to_local_port;
1906 mutex_unlock(&priv->reg_mutex);
1907 return 0;
1908 }
1909
1910 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1911 struct dsa_mall_mirror_tc_entry *mirror)
1912 {
1913 int group = 0;
1914 struct rtl838x_switch_priv *priv = ds->priv;
1915 int ctrl_reg, dpm_reg, spm_reg;
1916
1917 pr_debug("In %s\n", __func__);
1918 for (group = 0; group < 4; group++) {
1919 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1920 break;
1921 }
1922 if (group >= 4)
1923 return;
1924
1925 ctrl_reg = priv->r->mir_ctrl + group * 4;
1926 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1927 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1928
1929 mutex_lock(&priv->reg_mutex);
1930 if (mirror->ingress) {
1931 /* Ingress, clear source port matrix */
1932 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1933 } else {
1934 /* Egress, clear destination port matrix */
1935 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1936 }
1937
1938 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1939 priv->mirror_group_ports[group] = -1;
1940 sw_w32(0, ctrl_reg);
1941 }
1942
1943 mutex_unlock(&priv->reg_mutex);
1944 }
1945
1946 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1947 {
1948 struct rtl838x_switch_priv *priv = ds->priv;
1949 unsigned long features = 0;
1950 pr_debug("%s: %d %lX\n", __func__, port, flags);
1951 if (priv->r->enable_learning)
1952 features |= BR_LEARNING;
1953 if (priv->r->enable_flood)
1954 features |= BR_FLOOD;
1955 if (priv->r->enable_mcast_flood)
1956 features |= BR_MCAST_FLOOD;
1957 if (priv->r->enable_bcast_flood)
1958 features |= BR_BCAST_FLOOD;
1959 if (flags & ~(features))
1960 return -EINVAL;
1961
1962 return 0;
1963 }
1964
1965 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)
1966 {
1967 struct rtl838x_switch_priv *priv = ds->priv;
1968
1969 pr_debug("%s: %d %lX\n", __func__, port, flags);
1970 if (priv->r->enable_learning)
1971 priv->r->enable_learning(port, !!(flags & BR_LEARNING));
1972
1973 if (priv->r->enable_flood)
1974 priv->r->enable_flood(port, !!(flags & BR_FLOOD));
1975
1976 if (priv->r->enable_mcast_flood)
1977 priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));
1978
1979 if (priv->r->enable_bcast_flood)
1980 priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));
1981
1982 return 0;
1983 }
1984
1985 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1986 struct net_device *lag,
1987 struct netdev_lag_upper_info *info)
1988 {
1989 int id;
1990
1991 id = dsa_lag_id(ds->dst, lag);
1992 if (id < 0 || id >= ds->num_lag_ids)
1993 return false;
1994
1995 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1996 return false;
1997 }
1998 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
1999 return false;
2000
2001 return true;
2002 }
2003
2004 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
2005 {
2006 struct rtl838x_switch_priv *priv = ds->priv;
2007
2008 pr_debug("%s: %d\n", __func__, port);
2009 // Nothing to be done...
2010
2011 return 0;
2012 }
2013
2014 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2015 struct net_device *lag,
2016 struct netdev_lag_upper_info *info)
2017 {
2018 struct rtl838x_switch_priv *priv = ds->priv;
2019 int i, err = 0;
2020
2021 if (!rtl83xx_lag_can_offload(ds, lag, info))
2022 return -EOPNOTSUPP;
2023
2024 mutex_lock(&priv->reg_mutex);
2025
2026 for (i = 0; i < priv->n_lags; i++) {
2027 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2028 break;
2029 }
2030 if (port >= priv->cpu_port) {
2031 err = -EINVAL;
2032 goto out;
2033 }
2034 pr_info("port_lag_join: group %d, port %d\n",i, port);
2035 if (!priv->lag_devs[i])
2036 priv->lag_devs[i] = lag;
2037
2038 if (priv->lag_primary[i]==-1) {
2039 priv->lag_primary[i]=port;
2040 } else
2041 priv->is_lagmember[port] = 1;
2042
2043 priv->lagmembers |= (1ULL << port);
2044
2045 pr_debug("lag_members = %llX\n", priv->lagmembers);
2046 err = rtl83xx_lag_add(priv->ds, i, port, info);
2047 if (err) {
2048 err = -EINVAL;
2049 goto out;
2050 }
2051
2052 out:
2053 mutex_unlock(&priv->reg_mutex);
2054 return err;
2055
2056 }
2057
2058 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2059 struct net_device *lag)
2060 {
2061 int i, group = -1, err;
2062 struct rtl838x_switch_priv *priv = ds->priv;
2063
2064 mutex_lock(&priv->reg_mutex);
2065 for (i=0;i<priv->n_lags;i++) {
2066 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2067 group = i;
2068 break;
2069 }
2070 }
2071
2072 if (group == -1) {
2073 pr_info("port_lag_leave: port %d is not a member\n", port);
2074 err = -EINVAL;
2075 goto out;
2076 }
2077
2078 if (port >= priv->cpu_port) {
2079 err = -EINVAL;
2080 goto out;
2081 }
2082 pr_info("port_lag_del: group %d, port %d\n",group, port);
2083 priv->lagmembers &=~ (1ULL << port);
2084 priv->lag_primary[i] = -1;
2085 priv->is_lagmember[port] = 0;
2086 pr_debug("lag_members = %llX\n", priv->lagmembers);
2087 err = rtl83xx_lag_del(priv->ds, group, port);
2088 if (err) {
2089 err = -EINVAL;
2090 goto out;
2091 }
2092 if (!priv->lags_port_members[i])
2093 priv->lag_devs[i] = NULL;
2094
2095 out:
2096 mutex_unlock(&priv->reg_mutex);
2097 return 0;
2098 }
2099
2100 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2101 {
2102 u32 val;
2103 u32 offset = 0;
2104 struct rtl838x_switch_priv *priv = ds->priv;
2105
2106 if (phy_addr >= 24 && phy_addr <= 27
2107 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2108 if (phy_addr == 26)
2109 offset = 0x100;
2110 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2111 return val;
2112 }
2113
2114 read_phy(phy_addr, 0, phy_reg, &val);
2115 return val;
2116 }
2117
2118 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2119 {
2120 u32 offset = 0;
2121 struct rtl838x_switch_priv *priv = ds->priv;
2122
2123 if (phy_addr >= 24 && phy_addr <= 27
2124 && priv->ports[24].phy == PHY_RTL838X_SDS) {
2125 if (phy_addr == 26)
2126 offset = 0x100;
2127 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2128 return 0;
2129 }
2130 return write_phy(phy_addr, 0, phy_reg, val);
2131 }
2132
2133 const struct dsa_switch_ops rtl83xx_switch_ops = {
2134 .get_tag_protocol = rtl83xx_get_tag_protocol,
2135 .setup = rtl83xx_setup,
2136
2137 .phy_read = dsa_phy_read,
2138 .phy_write = dsa_phy_write,
2139
2140 .phylink_validate = rtl83xx_phylink_validate,
2141 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2142 .phylink_mac_config = rtl83xx_phylink_mac_config,
2143 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2144 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2145
2146 .get_strings = rtl83xx_get_strings,
2147 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2148 .get_sset_count = rtl83xx_get_sset_count,
2149
2150 .port_enable = rtl83xx_port_enable,
2151 .port_disable = rtl83xx_port_disable,
2152
2153 .get_mac_eee = rtl83xx_get_mac_eee,
2154 .set_mac_eee = rtl83xx_set_mac_eee,
2155
2156 .set_ageing_time = rtl83xx_set_ageing_time,
2157 .port_bridge_join = rtl83xx_port_bridge_join,
2158 .port_bridge_leave = rtl83xx_port_bridge_leave,
2159 .port_stp_state_set = rtl83xx_port_stp_state_set,
2160 .port_fast_age = rtl83xx_fast_age,
2161
2162 .port_vlan_filtering = rtl83xx_vlan_filtering,
2163 .port_vlan_prepare = rtl83xx_vlan_prepare,
2164 .port_vlan_add = rtl83xx_vlan_add,
2165 .port_vlan_del = rtl83xx_vlan_del,
2166
2167 .port_fdb_add = rtl83xx_port_fdb_add,
2168 .port_fdb_del = rtl83xx_port_fdb_del,
2169 .port_fdb_dump = rtl83xx_port_fdb_dump,
2170
2171 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2172 .port_mdb_add = rtl83xx_port_mdb_add,
2173 .port_mdb_del = rtl83xx_port_mdb_del,
2174
2175 .port_mirror_add = rtl83xx_port_mirror_add,
2176 .port_mirror_del = rtl83xx_port_mirror_del,
2177
2178 .port_lag_change = rtl83xx_port_lag_change,
2179 .port_lag_join = rtl83xx_port_lag_join,
2180 .port_lag_leave = rtl83xx_port_lag_leave,
2181
2182 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2183 .port_bridge_flags = rtl83xx_port_bridge_flags,
2184 };
2185
2186 const struct dsa_switch_ops rtl930x_switch_ops = {
2187 .get_tag_protocol = rtl83xx_get_tag_protocol,
2188 .setup = rtl93xx_setup,
2189
2190 .phy_read = dsa_phy_read,
2191 .phy_write = dsa_phy_write,
2192
2193 .phylink_validate = rtl93xx_phylink_validate,
2194 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2195 .phylink_mac_config = rtl93xx_phylink_mac_config,
2196 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2197 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2198
2199 .get_strings = rtl83xx_get_strings,
2200 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2201 .get_sset_count = rtl83xx_get_sset_count,
2202
2203 .port_enable = rtl83xx_port_enable,
2204 .port_disable = rtl83xx_port_disable,
2205
2206 .get_mac_eee = rtl93xx_get_mac_eee,
2207 .set_mac_eee = rtl83xx_set_mac_eee,
2208
2209 .set_ageing_time = rtl83xx_set_ageing_time,
2210 .port_bridge_join = rtl83xx_port_bridge_join,
2211 .port_bridge_leave = rtl83xx_port_bridge_leave,
2212 .port_stp_state_set = rtl83xx_port_stp_state_set,
2213 .port_fast_age = rtl930x_fast_age,
2214
2215 .port_vlan_filtering = rtl83xx_vlan_filtering,
2216 .port_vlan_prepare = rtl83xx_vlan_prepare,
2217 .port_vlan_add = rtl83xx_vlan_add,
2218 .port_vlan_del = rtl83xx_vlan_del,
2219
2220 .port_fdb_add = rtl83xx_port_fdb_add,
2221 .port_fdb_del = rtl83xx_port_fdb_del,
2222 .port_fdb_dump = rtl83xx_port_fdb_dump,
2223
2224 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
2225 .port_mdb_add = rtl83xx_port_mdb_add,
2226 .port_mdb_del = rtl83xx_port_mdb_del,
2227
2228 .port_lag_change = rtl83xx_port_lag_change,
2229 .port_lag_join = rtl83xx_port_lag_join,
2230 .port_lag_leave = rtl83xx_port_lag_leave,
2231
2232 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2233 .port_bridge_flags = rtl83xx_port_bridge_flags,
2234 };
OpenWrt Source Repository