1 /* SPDX-License-Identifier: GPL-2.0-only */
4 #include <linux/clockchips.h>
6 #include <linux/cpuhotplug.h>
7 #include <linux/interrupt.h>
8 #include <linux/sched_clock.h>
17 #define RTTM_CTRL_ENABLE BIT(28)
18 #define RTTM_INT_PENDING BIT(16)
19 #define RTTM_INT_ENABLE BIT(20)
22 * The Otto platform provides multiple 28 bit timers/counters with the following
23 * operating logic. If enabled the timer counts up. Per timer one can set a
24 * maximum counter value as an end marker. If end marker is reached the timer
25 * fires an interrupt. If the timer "overflows" by reaching the end marker or
26 * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and
27 * the timer is in operating mode COUNTER it stops. In mode TIMER it will
28 * continue to count up.
31 #define RTTM_CTRL_COUNTER 0
32 #define RTTM_CTRL_TIMER BIT(24)
34 #define RTTM_BIT_COUNT 28
35 #define RTTM_MIN_DELTA 8
36 #define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28)
39 * Timers are derived from the LXB clock frequency. Usually this is a fixed
40 * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that.
41 * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its
42 * base. The only meaningful frequencies we can achieve from that are 175.000
43 * MHz and 153.125 MHz. The greatest common divisor of all explained possible
44 * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
47 #define RTTM_TICKS_PER_SEC 3125000
51 struct clocksource cs
;
55 * Simple internal register functions
58 static inline void rttm_set_counter(void __iomem
*base
, unsigned int counter
)
60 iowrite32(counter
, base
+ RTTM_CNT
);
63 static inline unsigned int rttm_get_counter(void __iomem
*base
)
65 return ioread32(base
+ RTTM_CNT
);
68 static inline void rttm_set_period(void __iomem
*base
, unsigned int period
)
70 iowrite32(period
, base
+ RTTM_DATA
);
73 static inline void rttm_disable_timer(void __iomem
*base
)
75 iowrite32(0, base
+ RTTM_CTRL
);
78 static inline void rttm_enable_timer(void __iomem
*base
, u32 mode
, u32 divisor
)
80 iowrite32(RTTM_CTRL_ENABLE
| mode
| divisor
, base
+ RTTM_CTRL
);
83 static inline void rttm_ack_irq(void __iomem
*base
)
85 iowrite32(ioread32(base
+ RTTM_INT
) | RTTM_INT_PENDING
, base
+ RTTM_INT
);
88 static inline void rttm_enable_irq(void __iomem
*base
)
90 iowrite32(RTTM_INT_ENABLE
, base
+ RTTM_INT
);
93 static inline void rttm_disable_irq(void __iomem
*base
)
95 iowrite32(0, base
+ RTTM_INT
);
99 * Aggregated control functions for kernel clock framework
102 #define RTTM_DEBUG(base) \
103 pr_debug("------------- %s %d %08x\n", __func__, \
104 smp_processor_id(), (u32)base)
106 static irqreturn_t
rttm_timer_interrupt(int irq
, void *dev_id
)
108 struct clock_event_device
*clkevt
= dev_id
;
109 struct timer_of
*to
= to_timer_of(clkevt
);
111 rttm_ack_irq(to
->of_base
.base
);
112 RTTM_DEBUG(to
->of_base
.base
);
113 clkevt
->event_handler(clkevt
);
118 static void rttm_stop_timer(void __iomem
*base
)
120 rttm_disable_timer(base
);
124 static void rttm_start_timer(struct timer_of
*to
, u32 mode
)
126 rttm_set_counter(to
->of_base
.base
, 0);
127 rttm_enable_timer(to
->of_base
.base
, mode
, to
->of_clk
.rate
/ RTTM_TICKS_PER_SEC
);
130 static int rttm_next_event(unsigned long delta
, struct clock_event_device
*clkevt
)
132 struct timer_of
*to
= to_timer_of(clkevt
);
134 RTTM_DEBUG(to
->of_base
.base
);
135 rttm_stop_timer(to
->of_base
.base
);
136 rttm_set_period(to
->of_base
.base
, delta
);
137 rttm_start_timer(to
, RTTM_CTRL_COUNTER
);
142 static int rttm_state_oneshot(struct clock_event_device
*clkevt
)
144 struct timer_of
*to
= to_timer_of(clkevt
);
146 RTTM_DEBUG(to
->of_base
.base
);
147 rttm_stop_timer(to
->of_base
.base
);
148 rttm_set_period(to
->of_base
.base
, RTTM_TICKS_PER_SEC
/ HZ
);
149 rttm_start_timer(to
, RTTM_CTRL_COUNTER
);
154 static int rttm_state_periodic(struct clock_event_device
*clkevt
)
156 struct timer_of
*to
= to_timer_of(clkevt
);
158 RTTM_DEBUG(to
->of_base
.base
);
159 rttm_stop_timer(to
->of_base
.base
);
160 rttm_set_period(to
->of_base
.base
, RTTM_TICKS_PER_SEC
/ HZ
);
161 rttm_start_timer(to
, RTTM_CTRL_TIMER
);
166 static int rttm_state_shutdown(struct clock_event_device
*clkevt
)
168 struct timer_of
*to
= to_timer_of(clkevt
);
170 RTTM_DEBUG(to
->of_base
.base
);
171 rttm_stop_timer(to
->of_base
.base
);
176 static void rttm_setup_timer(void __iomem
*base
)
179 rttm_stop_timer(base
);
180 rttm_set_period(base
, 0);
183 static u64
rttm_read_clocksource(struct clocksource
*cs
)
185 struct rttm_cs
*rcs
= container_of(cs
, struct rttm_cs
, cs
);
187 return (u64
)rttm_get_counter(rcs
->to
.of_base
.base
);
191 * Module initialization part.
194 static DEFINE_PER_CPU(struct timer_of
, rttm_to
) = {
195 .flags
= TIMER_OF_BASE
| TIMER_OF_CLOCK
| TIMER_OF_IRQ
,
197 .flags
= IRQF_PERCPU
| IRQF_TIMER
,
198 .handler
= rttm_timer_interrupt
,
202 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
203 .set_state_periodic
= rttm_state_periodic
,
204 .set_state_shutdown
= rttm_state_shutdown
,
205 .set_state_oneshot
= rttm_state_oneshot
,
206 .set_next_event
= rttm_next_event
210 static int rttm_enable_clocksource(struct clocksource
*cs
)
212 struct rttm_cs
*rcs
= container_of(cs
, struct rttm_cs
, cs
);
214 rttm_disable_irq(rcs
->to
.of_base
.base
);
215 rttm_setup_timer(rcs
->to
.of_base
.base
);
216 rttm_enable_timer(rcs
->to
.of_base
.base
, RTTM_CTRL_TIMER
,
217 rcs
->to
.of_clk
.rate
/ RTTM_TICKS_PER_SEC
);
222 struct rttm_cs rttm_cs
= {
224 .flags
= TIMER_OF_BASE
| TIMER_OF_CLOCK
,
227 .name
= "realtek_otto_timer",
229 .mask
= CLOCKSOURCE_MASK(RTTM_BIT_COUNT
),
230 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
231 .read
= rttm_read_clocksource
,
232 .enable
= rttm_enable_clocksource
236 static u64 notrace
rttm_read_clock(void)
238 return (u64
)rttm_get_counter(rttm_cs
.to
.of_base
.base
);
241 static int rttm_cpu_starting(unsigned int cpu
)
243 struct timer_of
*to
= per_cpu_ptr(&rttm_to
, cpu
);
245 RTTM_DEBUG(to
->of_base
.base
);
246 to
->clkevt
.cpumask
= cpumask_of(cpu
);
247 irq_force_affinity(to
->of_irq
.irq
, to
->clkevt
.cpumask
);
248 clockevents_config_and_register(&to
->clkevt
, RTTM_TICKS_PER_SEC
,
249 RTTM_MIN_DELTA
, RTTM_MAX_DELTA
);
250 rttm_enable_irq(to
->of_base
.base
);
255 static int __init
rttm_probe(struct device_node
*np
)
257 int cpu
, cpu_rollback
;
259 int clkidx
= num_possible_cpus();
261 * Use the first n timers as per CPU clock event generators
263 for_each_possible_cpu(cpu
) {
264 to
= per_cpu_ptr(&rttm_to
, cpu
);
265 to
->of_irq
.index
= to
->of_base
.index
= cpu
;
266 if (timer_of_init(np
, to
)) {
267 pr_err("%s: setup of timer %d failed\n", __func__
, cpu
);
270 rttm_setup_timer(to
->of_base
.base
);
273 * Activate the n'th+1 timer as a stable CPU clocksource.
276 to
->of_base
.index
= clkidx
;
277 timer_of_init(np
, to
);
278 if (rttm_cs
.to
.of_base
.base
&& rttm_cs
.to
.of_clk
.rate
) {
279 clocksource_register_hz(&rttm_cs
.cs
, RTTM_TICKS_PER_SEC
);
280 sched_clock_register(rttm_read_clock
, RTTM_BIT_COUNT
, RTTM_TICKS_PER_SEC
);
282 pr_err("%s: setup of timer %d as clocksoure failed", __func__
, clkidx
);
284 return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING
,
285 "timer/realtek:online",
286 rttm_cpu_starting
, NULL
);
288 pr_err("%s: timer registration failed\n", __func__
);
289 for_each_possible_cpu(cpu_rollback
) {
290 if (cpu_rollback
== cpu
)
292 to
= per_cpu_ptr(&rttm_to
, cpu_rollback
);
293 timer_of_cleanup(to
);
299 TIMER_OF_DECLARE(otto_timer
, "realtek,otto-timer", rttm_probe
);