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realtek: Add missing headers
[openwrt/openwrt.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/etherdevice.h>
5 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7
8 #include "rtl83xx.h"
9
10 extern struct rtl83xx_soc_info soc_info;
11
12 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
13 {
14 mutex_lock(&priv->reg_mutex);
15
16 /* Enable statistics module: all counters plus debug.
17 * On RTL839x all counters are enabled by default
18 */
19 if (priv->family_id == RTL8380_FAMILY_ID)
20 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
21
22 /* Reset statistics counters */
23 sw_w32_mask(0, 1, priv->r->stat_rst);
24
25 mutex_unlock(&priv->reg_mutex);
26 }
27
28 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
29 {
30 u64 v = 0;
31
32 msleep(1000);
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (int i = 0; i < priv->cpu_port; i++) {
35 if (priv->ports[i].phy)
36 v |= BIT_ULL(i);
37 }
38
39 pr_info("%s: %16llx\n", __func__, v);
40 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
41
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
45 else if(priv->family_id == RTL9300_FAMILY_ID)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
47 }
48
49 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
96 };
97
98
99 /* DSA callbacks */
100
101
102 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
103 int port,
104 enum dsa_tag_protocol mprot)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /* Initialize all VLANS */
113 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
114 {
115 struct rtl838x_vlan_info info;
116
117 pr_info("In %s\n", __func__);
118
119 priv->r->vlan_profile_setup(0);
120 priv->r->vlan_profile_setup(1);
121 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
122 priv->r->vlan_profile_dump(0);
123
124 info.fid = 0; /* Default Forwarding ID / MSTI */
125 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
126 info.hash_mc_fid = false; /* Do the same for Multicast packets */
127 info.profile_id = 0; /* Use default Vlan Profile 0 */
128 info.tagged_ports = 0; /* Initially no port members */
129 if (priv->family_id == RTL9310_FAMILY_ID) {
130 info.if_id = 0;
131 info.multicast_grp_mask = 0;
132 info.l2_tunnel_list_id = -1;
133 }
134
135 /* Initialize all vlans 0-4095 */
136 for (int i = 0; i < MAX_VLANS; i ++)
137 priv->r->vlan_set_tagged(i, &info);
138
139 /* reset PVIDs; defaults to 1 on reset */
140 for (int i = 0; i <= priv->ds->num_ports; i++) {
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
142 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
145 }
146
147 /* Set forwarding action based on inner VLAN tag */
148 for (int i = 0; i < priv->cpu_port; i++)
149 priv->r->vlan_fwd_on_inner(i, true);
150 }
151
152 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
153 {
154 for (int i = 0; i < priv->cpu_port; i++)
155 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
156 }
157
158 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
159 int port, bool enable)
160 {
161 int shift = SALRN_PORT_SHIFT(port);
162 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
163
164 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
165 priv->r->l2_port_new_salrn(port));
166 }
167
168 static int rtl83xx_setup(struct dsa_switch *ds)
169 {
170 struct rtl838x_switch_priv *priv = ds->priv;
171
172 pr_debug("%s called\n", __func__);
173
174 /* Disable MAC polling the PHY so that we can start configuration */
175 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
176
177 for (int i = 0; i < ds->num_ports; i++)
178 priv->ports[i].enable = false;
179 priv->ports[priv->cpu_port].enable = true;
180
181 /* Configure ports so they are disabled by default, but once enabled
182 * they will work in isolated mode (only traffic between port and CPU).
183 */
184 for (int i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
187 priv->r->traffic_set(i, BIT_ULL(i));
188 }
189 }
190 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
191
192 /* For standalone ports, forward packets even if a static fdb
193 * entry for the source address exists on another port.
194 */
195 if (priv->r->set_static_move_action) {
196 for (int i = 0; i <= priv->cpu_port; i++)
197 priv->r->set_static_move_action(i, true);
198 }
199
200 if (priv->family_id == RTL8380_FAMILY_ID)
201 rtl838x_print_matrix();
202 else
203 rtl839x_print_matrix();
204
205 rtl83xx_init_stats(priv);
206
207 rtl83xx_vlan_setup(priv);
208
209 rtl83xx_setup_bpdu_traps(priv);
210
211 ds->configure_vlan_while_not_filtering = true;
212
213 priv->r->l2_learning_setup();
214
215 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
216 ds->assisted_learning_on_cpu_port = true;
217
218 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
219 * 0: FWD, 1: DROP, 2: TRAP2CPU
220 */
221 if (priv->family_id == RTL8380_FAMILY_ID)
222 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
223 else
224 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
225
226 /* Enable MAC Polling PHY again */
227 rtl83xx_enable_phy_polling(priv);
228 pr_debug("Please wait until PHY is settled\n");
229 msleep(1000);
230 priv->r->pie_init(priv);
231
232 return 0;
233 }
234
235 static int rtl93xx_setup(struct dsa_switch *ds)
236 {
237 struct rtl838x_switch_priv *priv = ds->priv;
238
239 pr_info("%s called\n", __func__);
240
241 /* Disable MAC polling the PHY so that we can start configuration */
242 if (priv->family_id == RTL9300_FAMILY_ID)
243 sw_w32(0, RTL930X_SMI_POLL_CTRL);
244
245 if (priv->family_id == RTL9310_FAMILY_ID) {
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
247 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
248 }
249
250 /* Disable all ports except CPU port */
251 for (int i = 0; i < ds->num_ports; i++)
252 priv->ports[i].enable = false;
253 priv->ports[priv->cpu_port].enable = true;
254
255 /* Configure ports so they are disabled by default, but once enabled
256 * they will work in isolated mode (only traffic between port and CPU).
257 */
258 for (int i = 0; i < priv->cpu_port; i++) {
259 if (priv->ports[i].phy) {
260 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
261 priv->r->traffic_set(i, BIT_ULL(i));
262 }
263 }
264 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
265
266 rtl930x_print_matrix();
267
268 /* TODO: Initialize statistics */
269
270 rtl83xx_vlan_setup(priv);
271
272 ds->configure_vlan_while_not_filtering = true;
273
274 priv->r->l2_learning_setup();
275
276 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
277 ds->assisted_learning_on_cpu_port = true;
278
279 rtl83xx_enable_phy_polling(priv);
280
281 priv->r->pie_init(priv);
282
283 priv->r->led_init(priv);
284
285 return 0;
286 }
287
288 static int rtl93xx_get_sds(struct phy_device *phydev)
289 {
290 struct device *dev = &phydev->mdio.dev;
291 struct device_node *dn;
292 u32 sds_num;
293
294 if (!dev)
295 return -1;
296 if (dev->of_node) {
297 dn = dev->of_node;
298 if (of_property_read_u32(dn, "sds", &sds_num))
299 sds_num = -1;
300 } else {
301 dev_err(dev, "No DT node.\n");
302 return -1;
303 }
304
305 return sds_num;
306 }
307
308 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
309 unsigned long *supported,
310 struct phylink_link_state *state)
311 {
312 struct rtl838x_switch_priv *priv = ds->priv;
313 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
314
315 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
316
317 if (!phy_interface_mode_is_rgmii(state->interface) &&
318 state->interface != PHY_INTERFACE_MODE_NA &&
319 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
320 state->interface != PHY_INTERFACE_MODE_MII &&
321 state->interface != PHY_INTERFACE_MODE_REVMII &&
322 state->interface != PHY_INTERFACE_MODE_GMII &&
323 state->interface != PHY_INTERFACE_MODE_QSGMII &&
324 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
325 state->interface != PHY_INTERFACE_MODE_SGMII) {
326 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
327 dev_err(ds->dev,
328 "Unsupported interface: %d for port %d\n",
329 state->interface, port);
330 return;
331 }
332
333 /* Allow all the expected bits */
334 phylink_set(mask, Autoneg);
335 phylink_set_port_modes(mask);
336 phylink_set(mask, Pause);
337 phylink_set(mask, Asym_Pause);
338
339 /* With the exclusion of MII and Reverse MII, we support Gigabit,
340 * including Half duplex
341 */
342 if (state->interface != PHY_INTERFACE_MODE_MII &&
343 state->interface != PHY_INTERFACE_MODE_REVMII) {
344 phylink_set(mask, 1000baseT_Full);
345 phylink_set(mask, 1000baseT_Half);
346 }
347
348 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
349 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
350 phylink_set(mask, 1000baseX_Full);
351
352 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
353 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
354 phylink_set(mask, 1000baseX_Full);
355
356 phylink_set(mask, 10baseT_Half);
357 phylink_set(mask, 10baseT_Full);
358 phylink_set(mask, 100baseT_Half);
359 phylink_set(mask, 100baseT_Full);
360
361 bitmap_and(supported, supported, mask,
362 __ETHTOOL_LINK_MODE_MASK_NBITS);
363 bitmap_and(state->advertising, state->advertising, mask,
364 __ETHTOOL_LINK_MODE_MASK_NBITS);
365 }
366
367 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
368 unsigned long *supported,
369 struct phylink_link_state *state)
370 {
371 struct rtl838x_switch_priv *priv = ds->priv;
372 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
373
374 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
375 phy_modes(state->interface));
376
377 if (!phy_interface_mode_is_rgmii(state->interface) &&
378 state->interface != PHY_INTERFACE_MODE_NA &&
379 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
380 state->interface != PHY_INTERFACE_MODE_MII &&
381 state->interface != PHY_INTERFACE_MODE_REVMII &&
382 state->interface != PHY_INTERFACE_MODE_GMII &&
383 state->interface != PHY_INTERFACE_MODE_QSGMII &&
384 state->interface != PHY_INTERFACE_MODE_XGMII &&
385 state->interface != PHY_INTERFACE_MODE_HSGMII &&
386 state->interface != PHY_INTERFACE_MODE_10GBASER &&
387 state->interface != PHY_INTERFACE_MODE_10GKR &&
388 state->interface != PHY_INTERFACE_MODE_USXGMII &&
389 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
390 state->interface != PHY_INTERFACE_MODE_SGMII) {
391 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
392 dev_err(ds->dev,
393 "Unsupported interface: %d for port %d\n",
394 state->interface, port);
395 return;
396 }
397
398 /* Allow all the expected bits */
399 phylink_set(mask, Autoneg);
400 phylink_set_port_modes(mask);
401 phylink_set(mask, Pause);
402 phylink_set(mask, Asym_Pause);
403
404 /* With the exclusion of MII and Reverse MII, we support Gigabit,
405 * including Half duplex
406 */
407 if (state->interface != PHY_INTERFACE_MODE_MII &&
408 state->interface != PHY_INTERFACE_MODE_REVMII) {
409 phylink_set(mask, 1000baseT_Full);
410 phylink_set(mask, 1000baseT_Half);
411 }
412
413 /* Internal phys of the RTL93xx family provide 10G */
414 if (priv->ports[port].phy_is_integrated &&
415 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
416 phylink_set(mask, 1000baseX_Full);
417 } else if (priv->ports[port].phy_is_integrated) {
418 phylink_set(mask, 1000baseX_Full);
419 phylink_set(mask, 10000baseKR_Full);
420 phylink_set(mask, 10000baseSR_Full);
421 phylink_set(mask, 10000baseCR_Full);
422 }
423 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
424 phylink_set(mask, 1000baseX_Full);
425 phylink_set(mask, 1000baseT_Full);
426 phylink_set(mask, 10000baseKR_Full);
427 phylink_set(mask, 10000baseT_Full);
428 phylink_set(mask, 10000baseSR_Full);
429 phylink_set(mask, 10000baseCR_Full);
430 }
431
432 if (state->interface == PHY_INTERFACE_MODE_USXGMII)
433 phylink_set(mask, 10000baseT_Full);
434
435 phylink_set(mask, 10baseT_Half);
436 phylink_set(mask, 10baseT_Full);
437 phylink_set(mask, 100baseT_Half);
438 phylink_set(mask, 100baseT_Full);
439
440 bitmap_and(supported, supported, mask,
441 __ETHTOOL_LINK_MODE_MASK_NBITS);
442 bitmap_and(state->advertising, state->advertising, mask,
443 __ETHTOOL_LINK_MODE_MASK_NBITS);
444 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
445 }
446
447 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
448 struct phylink_link_state *state)
449 {
450 struct rtl838x_switch_priv *priv = ds->priv;
451 u64 speed;
452 u64 link;
453
454 if (port < 0 || port > priv->cpu_port)
455 return -EINVAL;
456
457 state->link = 0;
458 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
459 if (link & BIT_ULL(port))
460 state->link = 1;
461 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
462
463 state->duplex = 0;
464 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
465 state->duplex = 1;
466
467 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
468 speed >>= (port % 16) << 1;
469 switch (speed & 0x3) {
470 case 0:
471 state->speed = SPEED_10;
472 break;
473 case 1:
474 state->speed = SPEED_100;
475 break;
476 case 2:
477 state->speed = SPEED_1000;
478 break;
479 case 3:
480 if (priv->family_id == RTL9300_FAMILY_ID
481 && (port == 24 || port == 26)) /* Internal serdes */
482 state->speed = SPEED_2500;
483 else
484 state->speed = SPEED_100; /* Is in fact 500Mbit */
485 }
486
487 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
488 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
489 state->pause |= MLO_PAUSE_RX;
490 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
491 state->pause |= MLO_PAUSE_TX;
492
493 return 1;
494 }
495
496 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
497 struct phylink_link_state *state)
498 {
499 struct rtl838x_switch_priv *priv = ds->priv;
500 u64 speed;
501 u64 link;
502 u64 media;
503
504 if (port < 0 || port > priv->cpu_port)
505 return -EINVAL;
506
507 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
508 * state needs to be read twice in order to read a correct result.
509 * This would not be necessary for ports connected e.g. to RTL8218D
510 * PHYs.
511 */
512 state->link = 0;
513 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
514 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
515 if (link & BIT_ULL(port))
516 state->link = 1;
517
518 if (priv->family_id == RTL9310_FAMILY_ID)
519 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
520
521 if (priv->family_id == RTL9300_FAMILY_ID)
522 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
523
524 if (media & BIT_ULL(port))
525 state->link = 1;
526
527 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
528 link & BIT_ULL(port), media);
529
530 state->duplex = 0;
531 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
532 state->duplex = 1;
533
534 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
535 speed >>= (port % 8) << 2;
536 switch (speed & 0xf) {
537 case 0:
538 state->speed = SPEED_10;
539 break;
540 case 1:
541 state->speed = SPEED_100;
542 break;
543 case 2:
544 case 7:
545 state->speed = SPEED_1000;
546 break;
547 case 4:
548 state->speed = SPEED_10000;
549 break;
550 case 5:
551 case 8:
552 state->speed = SPEED_2500;
553 break;
554 case 6:
555 state->speed = SPEED_5000;
556 break;
557 default:
558 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
559 }
560
561 if (priv->family_id == RTL9310_FAMILY_ID
562 && (port >= 52 || port <= 55)) { /* Internal serdes */
563 state->speed = SPEED_10000;
564 state->link = 1;
565 state->duplex = 1;
566 }
567
568 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
569 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
570 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
571 state->pause |= MLO_PAUSE_RX;
572 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
573 state->pause |= MLO_PAUSE_TX;
574
575 return 1;
576 }
577
578 static void rtl83xx_config_interface(int port, phy_interface_t interface)
579 {
580 u32 old, int_shift, sds_shift;
581
582 switch (port) {
583 case 24:
584 int_shift = 0;
585 sds_shift = 5;
586 break;
587 case 26:
588 int_shift = 3;
589 sds_shift = 0;
590 break;
591 default:
592 return;
593 }
594
595 old = sw_r32(RTL838X_SDS_MODE_SEL);
596 switch (interface) {
597 case PHY_INTERFACE_MODE_1000BASEX:
598 if ((old >> sds_shift & 0x1f) == 4)
599 return;
600 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
601 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
602 break;
603 case PHY_INTERFACE_MODE_SGMII:
604 if ((old >> sds_shift & 0x1f) == 2)
605 return;
606 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
607 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
608 break;
609 default:
610 return;
611 }
612 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
613 }
614
615 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
616 unsigned int mode,
617 const struct phylink_link_state *state)
618 {
619 struct rtl838x_switch_priv *priv = ds->priv;
620 u32 reg;
621 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
622
623 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
624
625 if (port == priv->cpu_port) {
626 /* Set Speed, duplex, flow control
627 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
628 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
629 * | MEDIA_SEL
630 */
631 if (priv->family_id == RTL8380_FAMILY_ID) {
632 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
633 /* allow CRC errors on CPU-port */
634 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
635 } else {
636 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
637 }
638 return;
639 }
640
641 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
642 /* Auto-Negotiation does not work for MAC in RTL8390 */
643 if (priv->family_id == RTL8380_FAMILY_ID) {
644 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
645 pr_debug("PHY autonegotiates\n");
646 reg |= RTL838X_NWAY_EN;
647 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
648 rtl83xx_config_interface(port, state->interface);
649 return;
650 }
651 }
652
653 if (mode != MLO_AN_FIXED)
654 pr_debug("Fixed state.\n");
655
656 /* Clear id_mode_dis bit, and the existing port mode, let
657 * RGMII_MODE_EN bet set by mac_link_{up,down} */
658 if (priv->family_id == RTL8380_FAMILY_ID) {
659 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
660 if (state->pause & MLO_PAUSE_TXRX_MASK) {
661 if (state->pause & MLO_PAUSE_TX)
662 reg |= RTL838X_TX_PAUSE_EN;
663 reg |= RTL838X_RX_PAUSE_EN;
664 }
665 } else if (priv->family_id == RTL8390_FAMILY_ID) {
666 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
667 if (state->pause & MLO_PAUSE_TXRX_MASK) {
668 if (state->pause & MLO_PAUSE_TX)
669 reg |= RTL839X_TX_PAUSE_EN;
670 reg |= RTL839X_RX_PAUSE_EN;
671 }
672 }
673
674
675 reg &= ~(3 << speed_bit);
676 switch (state->speed) {
677 case SPEED_1000:
678 reg |= 2 << speed_bit;
679 break;
680 case SPEED_100:
681 reg |= 1 << speed_bit;
682 break;
683 default:
684 break; /* Ignore, including 10MBit which has a speed value of 0 */
685 }
686
687 if (priv->family_id == RTL8380_FAMILY_ID) {
688 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
689 if (state->link)
690 reg |= RTL838X_FORCE_LINK_EN;
691 if (state->duplex == RTL838X_DUPLEX_MODE)
692 reg |= RTL838X_DUPLEX_MODE;
693 } else if (priv->family_id == RTL8390_FAMILY_ID) {
694 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
695 if (state->link)
696 reg |= RTL839X_FORCE_LINK_EN;
697 if (state->duplex == RTL839X_DUPLEX_MODE)
698 reg |= RTL839X_DUPLEX_MODE;
699 }
700
701 /* LAG members must use DUPLEX and we need to enable the link */
702 if (priv->lagmembers & BIT_ULL(port)) {
703 switch(priv->family_id) {
704 case RTL8380_FAMILY_ID:
705 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
706 break;
707 case RTL8390_FAMILY_ID:
708 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
709 break;
710 }
711 }
712
713 /* Disable AN */
714 if (priv->family_id == RTL8380_FAMILY_ID)
715 reg &= ~RTL838X_NWAY_EN;
716 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
717 }
718
719 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
720 unsigned int mode,
721 const struct phylink_link_state *state)
722 {
723 struct rtl838x_switch_priv *priv = ds->priv;
724 int sds_num;
725 u32 reg, band;
726
727 sds_num = priv->ports[port].sds_num;
728 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
729
730 switch (state->interface) {
731 case PHY_INTERFACE_MODE_HSGMII:
732 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
733 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
734 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
735 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
736 break;
737 case PHY_INTERFACE_MODE_1000BASEX:
738 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
739 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
740 break;
741 case PHY_INTERFACE_MODE_XGMII:
742 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
743 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
744 break;
745 case PHY_INTERFACE_MODE_10GBASER:
746 case PHY_INTERFACE_MODE_10GKR:
747 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
748 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
749 break;
750 case PHY_INTERFACE_MODE_USXGMII:
751 /* Translates to MII_USXGMII_10GSXGMII */
752 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
753 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
754 break;
755 case PHY_INTERFACE_MODE_SGMII:
756 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
757 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
758 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
759 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
760 break;
761 case PHY_INTERFACE_MODE_QSGMII:
762 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
763 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
764 break;
765 default:
766 pr_err("%s: unknown serdes mode: %s\n",
767 __func__, phy_modes(state->interface));
768 return;
769 }
770
771 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
772 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
773
774 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
775
776 reg &= ~(0xf << 12);
777 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
778
779 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
780
781 if (priv->lagmembers & BIT_ULL(port))
782 reg |= RTL931X_DUPLEX_MODE;
783
784 if (state->duplex == DUPLEX_FULL)
785 reg |= RTL931X_DUPLEX_MODE;
786
787 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
788
789 }
790
791 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
792 unsigned int mode,
793 const struct phylink_link_state *state)
794 {
795 struct rtl838x_switch_priv *priv = ds->priv;
796 int sds_num, sds_mode;
797 u32 reg;
798
799 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
800 port, mode, phy_modes(state->interface), state->speed, state->link);
801
802 /* Nothing to be done for the CPU-port */
803 if (port == priv->cpu_port)
804 return;
805
806 if (priv->family_id == RTL9310_FAMILY_ID)
807 return rtl931x_phylink_mac_config(ds, port, mode, state);
808
809 sds_num = priv->ports[port].sds_num;
810 pr_info("%s SDS is %d\n", __func__, sds_num);
811 if (sds_num >= 0) {
812 switch (state->interface) {
813 case PHY_INTERFACE_MODE_HSGMII:
814 sds_mode = 0x12;
815 break;
816 case PHY_INTERFACE_MODE_1000BASEX:
817 sds_mode = 0x04;
818 break;
819 case PHY_INTERFACE_MODE_XGMII:
820 sds_mode = 0x10;
821 break;
822 case PHY_INTERFACE_MODE_10GBASER:
823 case PHY_INTERFACE_MODE_10GKR:
824 sds_mode = 0x1b; /* 10G 1000X Auto */
825 break;
826 case PHY_INTERFACE_MODE_USXGMII:
827 sds_mode = 0x0d;
828 break;
829 default:
830 pr_err("%s: unknown serdes mode: %s\n",
831 __func__, phy_modes(state->interface));
832 return;
833 }
834 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
835 rtl9300_serdes_setup(sds_num, state->interface);
836 }
837
838 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
839 reg &= ~(0xf << 3);
840
841 switch (state->speed) {
842 case SPEED_10000:
843 reg |= 4 << 3;
844 break;
845 case SPEED_5000:
846 reg |= 6 << 3;
847 break;
848 case SPEED_2500:
849 reg |= 5 << 3;
850 break;
851 case SPEED_1000:
852 reg |= 2 << 3;
853 break;
854 default:
855 reg |= 2 << 3;
856 break;
857 }
858
859 if (state->link)
860 reg |= RTL930X_FORCE_LINK_EN;
861
862 if (priv->lagmembers & BIT_ULL(port))
863 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
864
865 if (state->duplex == DUPLEX_FULL)
866 reg |= RTL930X_DUPLEX_MODE;
867
868 if (priv->ports[port].phy_is_integrated)
869 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
870 else
871 reg |= RTL930X_FORCE_EN;
872
873 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
874 }
875
876 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
877 unsigned int mode,
878 phy_interface_t interface)
879 {
880 struct rtl838x_switch_priv *priv = ds->priv;
881
882 /* Stop TX/RX to port */
883 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
884
885 /* No longer force link */
886 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
887 }
888
889 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
890 unsigned int mode,
891 phy_interface_t interface)
892 {
893 struct rtl838x_switch_priv *priv = ds->priv;
894 u32 v = 0;
895
896 /* Stop TX/RX to port */
897 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
898
899 /* No longer force link */
900 if (priv->family_id == RTL9300_FAMILY_ID)
901 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
902 else if (priv->family_id == RTL9310_FAMILY_ID)
903 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
904 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
905 }
906
907 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
908 unsigned int mode,
909 phy_interface_t interface,
910 struct phy_device *phydev,
911 int speed, int duplex,
912 bool tx_pause, bool rx_pause)
913 {
914 struct rtl838x_switch_priv *priv = ds->priv;
915 /* Restart TX/RX to port */
916 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
917 /* TODO: Set speed/duplex/pauses */
918 }
919
920 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
921 unsigned int mode,
922 phy_interface_t interface,
923 struct phy_device *phydev,
924 int speed, int duplex,
925 bool tx_pause, bool rx_pause)
926 {
927 struct rtl838x_switch_priv *priv = ds->priv;
928
929 /* Restart TX/RX to port */
930 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
931 /* TODO: Set speed/duplex/pauses */
932 }
933
934 static void rtl83xx_get_strings(struct dsa_switch *ds,
935 int port, u32 stringset, u8 *data)
936 {
937 if (stringset != ETH_SS_STATS)
938 return;
939
940 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
941 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
942 ETH_GSTRING_LEN);
943 }
944
945 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
946 uint64_t *data)
947 {
948 struct rtl838x_switch_priv *priv = ds->priv;
949 const struct rtl83xx_mib_desc *mib;
950 u64 h;
951
952 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
953 mib = &rtl83xx_mib[i];
954
955 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
956 if (mib->size == 2) {
957 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
958 data[i] |= h << 32;
959 }
960 }
961 }
962
963 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
964 {
965 if (sset != ETH_SS_STATS)
966 return 0;
967
968 return ARRAY_SIZE(rtl83xx_mib);
969 }
970
971 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
972 {
973 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
974 u64 portmask;
975
976 if (mc_group >= MAX_MC_GROUPS - 1)
977 return -1;
978
979 set_bit(mc_group, priv->mc_group_bm);
980 portmask = BIT_ULL(port);
981 priv->r->write_mcast_pmask(mc_group, portmask);
982
983 return mc_group;
984 }
985
986 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
987 {
988 u64 portmask = priv->r->read_mcast_pmask(mc_group);
989
990 pr_debug("%s: %d\n", __func__, port);
991
992 portmask |= BIT_ULL(port);
993 priv->r->write_mcast_pmask(mc_group, portmask);
994
995 return portmask;
996 }
997
998 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
999 {
1000 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1001
1002 pr_debug("%s: %d\n", __func__, port);
1003
1004 portmask &= ~BIT_ULL(port);
1005 priv->r->write_mcast_pmask(mc_group, portmask);
1006 if (!portmask)
1007 clear_bit(mc_group, priv->mc_group_bm);
1008
1009 return portmask;
1010 }
1011
1012 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1013 struct phy_device *phydev)
1014 {
1015 struct rtl838x_switch_priv *priv = ds->priv;
1016 u64 v;
1017
1018 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1019 priv->ports[port].enable = true;
1020
1021 /* enable inner tagging on egress, do not keep any tags */
1022 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1023
1024 if (dsa_is_cpu_port(ds, port))
1025 return 0;
1026
1027 /* add port to switch mask of CPU_PORT */
1028 priv->r->traffic_enable(priv->cpu_port, port);
1029
1030 if (priv->is_lagmember[port]) {
1031 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1032 return 0;
1033 }
1034
1035 /* add all other ports in the same bridge to switch mask of port */
1036 v = priv->r->traffic_get(port);
1037 v |= priv->ports[port].pm;
1038 priv->r->traffic_set(port, v);
1039
1040 /* TODO: Figure out if this is necessary */
1041 if (priv->family_id == RTL9300_FAMILY_ID) {
1042 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1043 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1044 }
1045
1046 if (priv->ports[port].sds_num < 0)
1047 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1048
1049 return 0;
1050 }
1051
1052 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1053 {
1054 struct rtl838x_switch_priv *priv = ds->priv;
1055 u64 v;
1056
1057 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1058 /* you can only disable user ports */
1059 if (!dsa_is_user_port(ds, port))
1060 return;
1061
1062 /* BUG: This does not work on RTL931X */
1063 /* remove port from switch mask of CPU_PORT */
1064 priv->r->traffic_disable(priv->cpu_port, port);
1065
1066 /* remove all other ports in the same bridge from switch mask of port */
1067 v = priv->r->traffic_get(port);
1068 v &= ~priv->ports[port].pm;
1069 priv->r->traffic_set(port, v);
1070
1071 priv->ports[port].enable = false;
1072 }
1073
1074 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1075 struct ethtool_eee *e)
1076 {
1077 struct rtl838x_switch_priv *priv = ds->priv;
1078
1079 if (e->eee_enabled && !priv->eee_enabled) {
1080 pr_info("Globally enabling EEE\n");
1081 priv->r->init_eee(priv, true);
1082 }
1083
1084 priv->r->port_eee_set(priv, port, e->eee_enabled);
1085
1086 if (e->eee_enabled)
1087 pr_info("Enabled EEE for port %d\n", port);
1088 else
1089 pr_info("Disabled EEE for port %d\n", port);
1090
1091 return 0;
1092 }
1093
1094 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1095 struct ethtool_eee *e)
1096 {
1097 struct rtl838x_switch_priv *priv = ds->priv;
1098
1099 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1100
1101 priv->r->eee_port_ability(priv, e, port);
1102
1103 e->eee_enabled = priv->ports[port].eee_enabled;
1104
1105 e->eee_active = !!(e->advertised & e->lp_advertised);
1106
1107 return 0;
1108 }
1109
1110 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1111 struct ethtool_eee *e)
1112 {
1113 struct rtl838x_switch_priv *priv = ds->priv;
1114
1115 e->supported = SUPPORTED_100baseT_Full |
1116 SUPPORTED_1000baseT_Full |
1117 SUPPORTED_2500baseX_Full;
1118
1119 priv->r->eee_port_ability(priv, e, port);
1120
1121 e->eee_enabled = priv->ports[port].eee_enabled;
1122
1123 e->eee_active = !!(e->advertised & e->lp_advertised);
1124
1125 return 0;
1126 }
1127
1128 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1129 {
1130 struct rtl838x_switch_priv *priv = ds->priv;
1131
1132 priv->r->set_ageing_time(msec);
1133
1134 return 0;
1135 }
1136
1137 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1138 struct net_device *bridge)
1139 {
1140 struct rtl838x_switch_priv *priv = ds->priv;
1141 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1142
1143 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1144
1145 if (priv->is_lagmember[port]) {
1146 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1147 return 0;
1148 }
1149
1150 mutex_lock(&priv->reg_mutex);
1151 for (int i = 0; i < ds->num_ports; i++) {
1152 /* Add this port to the port matrix of the other ports in the
1153 * same bridge. If the port is disabled, port matrix is kept
1154 * and not being setup until the port becomes enabled.
1155 */
1156 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1157 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1158 continue;
1159 if (priv->ports[i].enable)
1160 priv->r->traffic_enable(i, port);
1161
1162 priv->ports[i].pm |= BIT_ULL(port);
1163 port_bitmap |= BIT_ULL(i);
1164 }
1165 }
1166
1167 /* Add all other ports to this port matrix. */
1168 if (priv->ports[port].enable) {
1169 priv->r->traffic_enable(priv->cpu_port, port);
1170 v = priv->r->traffic_get(port);
1171 v |= port_bitmap;
1172 priv->r->traffic_set(port, v);
1173 }
1174 priv->ports[port].pm |= port_bitmap;
1175
1176 if (priv->r->set_static_move_action)
1177 priv->r->set_static_move_action(port, false);
1178
1179 mutex_unlock(&priv->reg_mutex);
1180
1181 return 0;
1182 }
1183
1184 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1185 struct net_device *bridge)
1186 {
1187 struct rtl838x_switch_priv *priv = ds->priv;
1188 u64 port_bitmap = 0, v;
1189
1190 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1191 mutex_lock(&priv->reg_mutex);
1192 for (int i = 0; i < ds->num_ports; i++) {
1193 /* Remove this port from the port matrix of the other ports
1194 * in the same bridge. If the port is disabled, port matrix
1195 * is kept and not being setup until the port becomes enabled.
1196 * And the other port's port matrix cannot be broken when the
1197 * other port is still a VLAN-aware port.
1198 */
1199 if (dsa_is_user_port(ds, i) && i != port) {
1200 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1201 continue;
1202 if (priv->ports[i].enable)
1203 priv->r->traffic_disable(i, port);
1204
1205 priv->ports[i].pm &= ~BIT_ULL(port);
1206 port_bitmap |= BIT_ULL(i);
1207 }
1208 }
1209
1210 /* Remove all other ports from this port matrix. */
1211 if (priv->ports[port].enable) {
1212 v = priv->r->traffic_get(port);
1213 v &= ~port_bitmap;
1214 priv->r->traffic_set(port, v);
1215 }
1216 priv->ports[port].pm &= ~port_bitmap;
1217
1218 if (priv->r->set_static_move_action)
1219 priv->r->set_static_move_action(port, true);
1220
1221 mutex_unlock(&priv->reg_mutex);
1222 }
1223
1224 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1225 {
1226 u32 msti = 0;
1227 u32 port_state[4];
1228 int index, bit;
1229 int pos = port;
1230 struct rtl838x_switch_priv *priv = ds->priv;
1231 int n = priv->port_width << 1;
1232
1233 /* Ports above or equal CPU port can never be configured */
1234 if (port >= priv->cpu_port)
1235 return;
1236
1237 mutex_lock(&priv->reg_mutex);
1238
1239 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1240 * have 64 bit fields, 839x and 931x have 128 bit fields
1241 */
1242 if (priv->family_id == RTL8390_FAMILY_ID)
1243 pos += 12;
1244 if (priv->family_id == RTL9300_FAMILY_ID)
1245 pos += 3;
1246 if (priv->family_id == RTL9310_FAMILY_ID)
1247 pos += 8;
1248
1249 index = n - (pos >> 4) - 1;
1250 bit = (pos << 1) % 32;
1251
1252 priv->r->stp_get(priv, msti, port_state);
1253
1254 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1255 port_state[index] &= ~(3 << bit);
1256
1257 switch (state) {
1258 case BR_STATE_DISABLED: /* 0 */
1259 port_state[index] |= (0 << bit);
1260 break;
1261 case BR_STATE_BLOCKING: /* 4 */
1262 case BR_STATE_LISTENING: /* 1 */
1263 port_state[index] |= (1 << bit);
1264 break;
1265 case BR_STATE_LEARNING: /* 2 */
1266 port_state[index] |= (2 << bit);
1267 break;
1268 case BR_STATE_FORWARDING: /* 3 */
1269 port_state[index] |= (3 << bit);
1270 default:
1271 break;
1272 }
1273
1274 priv->r->stp_set(priv, msti, port_state);
1275
1276 mutex_unlock(&priv->reg_mutex);
1277 }
1278
1279 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1280 {
1281 struct rtl838x_switch_priv *priv = ds->priv;
1282 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1283
1284 pr_debug("FAST AGE port %d\n", port);
1285 mutex_lock(&priv->reg_mutex);
1286 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1287 * port fields:
1288 * 0-4: Replacing port
1289 * 5-9: Flushed/replaced port
1290 * 10-21: FVID
1291 * 22: Entry types: 1: dynamic, 0: also static
1292 * 23: Match flush port
1293 * 24: Match FVID
1294 * 25: Flush (0) or replace (1) L2 entries
1295 * 26: Status of action (1: Start, 0: Done)
1296 */
1297 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1298
1299 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1300
1301 mutex_unlock(&priv->reg_mutex);
1302 }
1303
1304 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1305 {
1306 struct rtl838x_switch_priv *priv = ds->priv;
1307
1308 pr_info("%s port %d\n", __func__, port);
1309 mutex_lock(&priv->reg_mutex);
1310 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1311
1312 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1313
1314 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1315
1316 mutex_unlock(&priv->reg_mutex);
1317 }
1318
1319 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1320 {
1321 struct rtl838x_switch_priv *priv = ds->priv;
1322
1323 if (priv->family_id == RTL9310_FAMILY_ID)
1324 return rtl931x_fast_age(ds, port);
1325
1326 pr_debug("FAST AGE port %d\n", port);
1327 mutex_lock(&priv->reg_mutex);
1328 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1329
1330 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1331
1332 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1333
1334 mutex_unlock(&priv->reg_mutex);
1335 }
1336
1337 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1338 bool vlan_filtering,
1339 struct netlink_ext_ack *extack)
1340 {
1341 struct rtl838x_switch_priv *priv = ds->priv;
1342
1343 pr_debug("%s: port %d\n", __func__, port);
1344 mutex_lock(&priv->reg_mutex);
1345
1346 if (vlan_filtering) {
1347 /* Enable ingress and egress filtering
1348 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1349 * the filter action:
1350 * 0: Always Forward
1351 * 1: Drop packet
1352 * 2: Trap packet to CPU port
1353 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1354 */
1355 if (port != priv->cpu_port)
1356 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1357
1358 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1359 } else {
1360 /* Disable ingress and egress filtering */
1361 if (port != priv->cpu_port)
1362 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1363
1364 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1365 }
1366
1367 /* Do we need to do something to the CPU-Port, too? */
1368 mutex_unlock(&priv->reg_mutex);
1369
1370 return 0;
1371 }
1372
1373 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1374 const struct switchdev_obj_port_vlan *vlan)
1375 {
1376 struct rtl838x_vlan_info info;
1377 struct rtl838x_switch_priv *priv = ds->priv;
1378
1379 priv->r->vlan_tables_read(0, &info);
1380
1381 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1382 info.tagged_ports, info.untagged_ports, info.profile_id,
1383 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1384
1385 priv->r->vlan_tables_read(1, &info);
1386 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1387 info.tagged_ports, info.untagged_ports, info.profile_id,
1388 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1389 priv->r->vlan_set_untagged(1, info.untagged_ports);
1390 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1391
1392 priv->r->vlan_set_tagged(1, &info);
1393 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1394
1395 return 0;
1396 }
1397
1398 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1399 int port, int pvid)
1400 {
1401 /* Set both inner and outer PVID of the port */
1402 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1403 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1404 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1405 PBVLAN_MODE_UNTAG_AND_PRITAG);
1406 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1407 PBVLAN_MODE_UNTAG_AND_PRITAG);
1408
1409 priv->ports[port].pvid = pvid;
1410 }
1411
1412 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1413 const struct switchdev_obj_port_vlan *vlan,
1414 struct netlink_ext_ack *extack)
1415 {
1416 struct rtl838x_vlan_info info;
1417 struct rtl838x_switch_priv *priv = ds->priv;
1418 int err;
1419
1420 pr_debug("%s port %d, vid %d, flags %x\n",
1421 __func__, port, vlan->vid, vlan->flags);
1422
1423 if (vlan->vid > 4095) {
1424 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1425 return -ENOTSUPP;
1426 }
1427
1428 err = rtl83xx_vlan_prepare(ds, port, vlan);
1429 if (err)
1430 return err;
1431
1432 mutex_lock(&priv->reg_mutex);
1433
1434 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1435 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1436 else if (priv->ports[port].pvid == vlan->vid)
1437 rtl83xx_vlan_set_pvid(priv, port, 0);
1438
1439 /* Get port memberships of this vlan */
1440 priv->r->vlan_tables_read(vlan->vid, &info);
1441
1442 /* new VLAN? */
1443 if (!info.tagged_ports) {
1444 info.fid = 0;
1445 info.hash_mc_fid = false;
1446 info.hash_uc_fid = false;
1447 info.profile_id = 0;
1448 }
1449
1450 /* sanitize untagged_ports - must be a subset */
1451 if (info.untagged_ports & ~info.tagged_ports)
1452 info.untagged_ports = 0;
1453
1454 info.tagged_ports |= BIT_ULL(port);
1455 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1456 info.untagged_ports |= BIT_ULL(port);
1457 else
1458 info.untagged_ports &= ~BIT_ULL(port);
1459
1460 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1461 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1462
1463 priv->r->vlan_set_tagged(vlan->vid, &info);
1464 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1465
1466 mutex_unlock(&priv->reg_mutex);
1467
1468 return 0;
1469 }
1470
1471 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1472 const struct switchdev_obj_port_vlan *vlan)
1473 {
1474 struct rtl838x_vlan_info info;
1475 struct rtl838x_switch_priv *priv = ds->priv;
1476 u16 pvid;
1477
1478 pr_debug("%s: port %d, vid %d, flags %x\n",
1479 __func__, port, vlan->vid, vlan->flags);
1480
1481 if (vlan->vid > 4095) {
1482 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1483 return -ENOTSUPP;
1484 }
1485
1486 mutex_lock(&priv->reg_mutex);
1487 pvid = priv->ports[port].pvid;
1488
1489 /* Reset to default if removing the current PVID */
1490 if (vlan->vid == pvid) {
1491 rtl83xx_vlan_set_pvid(priv, port, 0);
1492 }
1493 /* Get port memberships of this vlan */
1494 priv->r->vlan_tables_read(vlan->vid, &info);
1495
1496 /* remove port from both tables */
1497 info.untagged_ports &= (~BIT_ULL(port));
1498 info.tagged_ports &= (~BIT_ULL(port));
1499
1500 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1501 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1502
1503 priv->r->vlan_set_tagged(vlan->vid, &info);
1504 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1505
1506 mutex_unlock(&priv->reg_mutex);
1507
1508 return 0;
1509 }
1510
1511 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1512 {
1513 memset(e, 0, sizeof(*e));
1514
1515 e->type = L2_UNICAST;
1516 e->valid = true;
1517
1518 e->age = 3;
1519 e->is_static = true;
1520
1521 e->port = port;
1522
1523 e->rvid = e->vid = vid;
1524 e->is_ip_mc = e->is_ipv6_mc = false;
1525 u64_to_ether_addr(mac, e->mac);
1526 }
1527
1528 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1529 {
1530 memset(e, 0, sizeof(*e));
1531
1532 e->type = L2_MULTICAST;
1533 e->valid = true;
1534
1535 e->mc_portmask_index = mc_group;
1536
1537 e->rvid = e->vid = vid;
1538 e->is_ip_mc = e->is_ipv6_mc = false;
1539 u64_to_ether_addr(mac, e->mac);
1540 }
1541
1542 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1543 * over the entries in the bucket until either a matching entry is found or an empty slot
1544 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1545 * when an empty slot was found and must exist is false, the index of the slot is returned
1546 * when no slots are available returns -1
1547 */
1548 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1549 bool must_exist, struct rtl838x_l2_entry *e)
1550 {
1551 int idx = -1;
1552 u32 key = priv->r->l2_hash_key(priv, seed);
1553 u64 entry;
1554
1555 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1556 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1557 for (int i = 0; i < priv->l2_bucket_size; i++) {
1558 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1559 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1560 if (must_exist && !e->valid)
1561 continue;
1562 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1563 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1564 break;
1565 }
1566 }
1567
1568 return idx;
1569 }
1570
1571 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1572 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1573 * when an empty slot was found the index of the slot is returned
1574 * when no slots are available returns -1
1575 */
1576 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1577 bool must_exist, struct rtl838x_l2_entry *e)
1578 {
1579 int idx = -1;
1580 u64 entry;
1581
1582 for (int i = 0; i < 64; i++) {
1583 entry = priv->r->read_cam(i, e);
1584 if (!must_exist && !e->valid) {
1585 if (idx < 0) /* First empty entry? */
1586 idx = i;
1587 break;
1588 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1589 pr_debug("Found entry in CAM\n");
1590 idx = i;
1591 break;
1592 }
1593 }
1594
1595 return idx;
1596 }
1597
1598 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1599 const unsigned char *addr, u16 vid)
1600 {
1601 struct rtl838x_switch_priv *priv = ds->priv;
1602 u64 mac = ether_addr_to_u64(addr);
1603 struct rtl838x_l2_entry e;
1604 int err = 0, idx;
1605 u64 seed = priv->r->l2_hash_seed(mac, vid);
1606
1607 if (priv->is_lagmember[port]) {
1608 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1609 return 0;
1610 }
1611
1612 mutex_lock(&priv->reg_mutex);
1613
1614 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1615
1616 /* Found an existing or empty entry */
1617 if (idx >= 0) {
1618 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1619 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1620 goto out;
1621 }
1622
1623 /* Hash buckets full, try CAM */
1624 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1625
1626 if (idx >= 0) {
1627 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1628 priv->r->write_cam(idx, &e);
1629 goto out;
1630 }
1631
1632 err = -ENOTSUPP;
1633
1634 out:
1635 mutex_unlock(&priv->reg_mutex);
1636
1637 return err;
1638 }
1639
1640 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1641 const unsigned char *addr, u16 vid)
1642 {
1643 struct rtl838x_switch_priv *priv = ds->priv;
1644 u64 mac = ether_addr_to_u64(addr);
1645 struct rtl838x_l2_entry e;
1646 int err = 0, idx;
1647 u64 seed = priv->r->l2_hash_seed(mac, vid);
1648
1649 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1650 mutex_lock(&priv->reg_mutex);
1651
1652 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1653
1654 if (idx >= 0) {
1655 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1656 e.valid = false;
1657 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1658 goto out;
1659 }
1660
1661 /* Check CAM for spillover from hash buckets */
1662 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1663
1664 if (idx >= 0) {
1665 e.valid = false;
1666 priv->r->write_cam(idx, &e);
1667 goto out;
1668 }
1669 err = -ENOENT;
1670
1671 out:
1672 mutex_unlock(&priv->reg_mutex);
1673
1674 return err;
1675 }
1676
1677 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1678 dsa_fdb_dump_cb_t *cb, void *data)
1679 {
1680 struct rtl838x_l2_entry e;
1681 struct rtl838x_switch_priv *priv = ds->priv;
1682
1683 mutex_lock(&priv->reg_mutex);
1684
1685 for (int i = 0; i < priv->fib_entries; i++) {
1686 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1687
1688 if (!e.valid)
1689 continue;
1690
1691 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1692 cb(e.mac, e.vid, e.is_static, data);
1693
1694 if (!((i + 1) % 64))
1695 cond_resched();
1696 }
1697
1698 for (int i = 0; i < 64; i++) {
1699 priv->r->read_cam(i, &e);
1700
1701 if (!e.valid)
1702 continue;
1703
1704 if (e.port == port)
1705 cb(e.mac, e.vid, e.is_static, data);
1706 }
1707
1708 mutex_unlock(&priv->reg_mutex);
1709
1710 return 0;
1711 }
1712
1713 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1714 const struct switchdev_obj_port_mdb *mdb)
1715 {
1716 struct rtl838x_switch_priv *priv = ds->priv;
1717 u64 mac = ether_addr_to_u64(mdb->addr);
1718 struct rtl838x_l2_entry e;
1719 int err = 0, idx;
1720 int vid = mdb->vid;
1721 u64 seed = priv->r->l2_hash_seed(mac, vid);
1722 int mc_group;
1723
1724 if (priv->id >= 0x9300)
1725 return -EOPNOTSUPP;
1726
1727 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1728
1729 if (priv->is_lagmember[port]) {
1730 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1731 return -EINVAL;
1732 }
1733
1734 mutex_lock(&priv->reg_mutex);
1735
1736 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1737
1738 /* Found an existing or empty entry */
1739 if (idx >= 0) {
1740 if (e.valid) {
1741 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1742 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1743 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1744 } else {
1745 pr_debug("New entry for seed %016llx\n", seed);
1746 mc_group = rtl83xx_mc_group_alloc(priv, port);
1747 if (mc_group < 0) {
1748 err = -ENOTSUPP;
1749 goto out;
1750 }
1751 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1752 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1753 }
1754 goto out;
1755 }
1756
1757 /* Hash buckets full, try CAM */
1758 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1759
1760 if (idx >= 0) {
1761 if (e.valid) {
1762 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1763 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1764 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1765 } else {
1766 pr_debug("New entry\n");
1767 mc_group = rtl83xx_mc_group_alloc(priv, port);
1768 if (mc_group < 0) {
1769 err = -ENOTSUPP;
1770 goto out;
1771 }
1772 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1773 priv->r->write_cam(idx, &e);
1774 }
1775 goto out;
1776 }
1777
1778 err = -ENOTSUPP;
1779
1780 out:
1781 mutex_unlock(&priv->reg_mutex);
1782 if (err)
1783 dev_err(ds->dev, "failed to add MDB entry\n");
1784
1785 return err;
1786 }
1787
1788 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1789 const struct switchdev_obj_port_mdb *mdb)
1790 {
1791 struct rtl838x_switch_priv *priv = ds->priv;
1792 u64 mac = ether_addr_to_u64(mdb->addr);
1793 struct rtl838x_l2_entry e;
1794 int err = 0, idx;
1795 int vid = mdb->vid;
1796 u64 seed = priv->r->l2_hash_seed(mac, vid);
1797 u64 portmask;
1798
1799 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1800
1801 if (priv->is_lagmember[port]) {
1802 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1803 return 0;
1804 }
1805
1806 mutex_lock(&priv->reg_mutex);
1807
1808 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1809
1810 if (idx >= 0) {
1811 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1812 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1813 if (!portmask) {
1814 e.valid = false;
1815 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1816 }
1817 goto out;
1818 }
1819
1820 /* Check CAM for spillover from hash buckets */
1821 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1822
1823 if (idx >= 0) {
1824 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1825 if (!portmask) {
1826 e.valid = false;
1827 priv->r->write_cam(idx, &e);
1828 }
1829 goto out;
1830 }
1831 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1832
1833 out:
1834 mutex_unlock(&priv->reg_mutex);
1835
1836 return err;
1837 }
1838
1839 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1840 struct dsa_mall_mirror_tc_entry *mirror,
1841 bool ingress)
1842 {
1843 /* We support 4 mirror groups, one destination port per group */
1844 int group;
1845 struct rtl838x_switch_priv *priv = ds->priv;
1846 int ctrl_reg, dpm_reg, spm_reg;
1847
1848 pr_debug("In %s\n", __func__);
1849
1850 for (group = 0; group < 4; group++) {
1851 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1852 break;
1853 }
1854 if (group >= 4) {
1855 for (group = 0; group < 4; group++) {
1856 if (priv->mirror_group_ports[group] < 0)
1857 break;
1858 }
1859 }
1860
1861 if (group >= 4)
1862 return -ENOSPC;
1863
1864 ctrl_reg = priv->r->mir_ctrl + group * 4;
1865 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1866 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1867
1868 pr_debug("Using group %d\n", group);
1869 mutex_lock(&priv->reg_mutex);
1870
1871 if (priv->family_id == RTL8380_FAMILY_ID) {
1872 /* Enable mirroring to port across VLANs (bit 11) */
1873 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1874 } else {
1875 /* Enable mirroring to destination port */
1876 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1877 }
1878
1879 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1880 mutex_unlock(&priv->reg_mutex);
1881 return -EEXIST;
1882 }
1883 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1884 mutex_unlock(&priv->reg_mutex);
1885 return -EEXIST;
1886 }
1887
1888 if (ingress)
1889 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1890 else
1891 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1892
1893 priv->mirror_group_ports[group] = mirror->to_local_port;
1894 mutex_unlock(&priv->reg_mutex);
1895
1896 return 0;
1897 }
1898
1899 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1900 struct dsa_mall_mirror_tc_entry *mirror)
1901 {
1902 int group = 0;
1903 struct rtl838x_switch_priv *priv = ds->priv;
1904 int ctrl_reg, dpm_reg, spm_reg;
1905
1906 pr_debug("In %s\n", __func__);
1907 for (group = 0; group < 4; group++) {
1908 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1909 break;
1910 }
1911 if (group >= 4)
1912 return;
1913
1914 ctrl_reg = priv->r->mir_ctrl + group * 4;
1915 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1916 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1917
1918 mutex_lock(&priv->reg_mutex);
1919 if (mirror->ingress) {
1920 /* Ingress, clear source port matrix */
1921 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1922 } else {
1923 /* Egress, clear destination port matrix */
1924 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1925 }
1926
1927 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1928 priv->mirror_group_ports[group] = -1;
1929 sw_w32(0, ctrl_reg);
1930 }
1931
1932 mutex_unlock(&priv->reg_mutex);
1933 }
1934
1935 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1936 {
1937 struct rtl838x_switch_priv *priv = ds->priv;
1938 unsigned long features = 0;
1939 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1940 if (priv->r->enable_learning)
1941 features |= BR_LEARNING;
1942 if (priv->r->enable_flood)
1943 features |= BR_FLOOD;
1944 if (priv->r->enable_mcast_flood)
1945 features |= BR_MCAST_FLOOD;
1946 if (priv->r->enable_bcast_flood)
1947 features |= BR_BCAST_FLOOD;
1948 if (flags.mask & ~(features))
1949 return -EINVAL;
1950
1951 return 0;
1952 }
1953
1954 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1955 {
1956 struct rtl838x_switch_priv *priv = ds->priv;
1957
1958 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1959 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1960 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1961
1962 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1963 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1964
1965 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1966 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1967
1968 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1969 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1970
1971 return 0;
1972 }
1973
1974 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1975 struct net_device *lag,
1976 struct netdev_lag_upper_info *info)
1977 {
1978 int id;
1979
1980 id = dsa_lag_id(ds->dst, lag);
1981 if (id < 0 || id >= ds->num_lag_ids)
1982 return false;
1983
1984 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1985 return false;
1986 }
1987 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
1988 return false;
1989
1990 return true;
1991 }
1992
1993 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
1994 {
1995 pr_debug("%s: %d\n", __func__, port);
1996 /* Nothing to be done... */
1997
1998 return 0;
1999 }
2000
2001 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2002 struct net_device *lag,
2003 struct netdev_lag_upper_info *info)
2004 {
2005 struct rtl838x_switch_priv *priv = ds->priv;
2006 int i, err = 0;
2007
2008 if (!rtl83xx_lag_can_offload(ds, lag, info))
2009 return -EOPNOTSUPP;
2010
2011 mutex_lock(&priv->reg_mutex);
2012
2013 for (i = 0; i < priv->n_lags; i++) {
2014 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2015 break;
2016 }
2017 if (port >= priv->cpu_port) {
2018 err = -EINVAL;
2019 goto out;
2020 }
2021 pr_info("port_lag_join: group %d, port %d\n",i, port);
2022 if (!priv->lag_devs[i])
2023 priv->lag_devs[i] = lag;
2024
2025 if (priv->lag_primary[i] == -1) {
2026 priv->lag_primary[i] = port;
2027 } else
2028 priv->is_lagmember[port] = 1;
2029
2030 priv->lagmembers |= (1ULL << port);
2031
2032 pr_debug("lag_members = %llX\n", priv->lagmembers);
2033 err = rtl83xx_lag_add(priv->ds, i, port, info);
2034 if (err) {
2035 err = -EINVAL;
2036 goto out;
2037 }
2038
2039 out:
2040 mutex_unlock(&priv->reg_mutex);
2041
2042 return err;
2043 }
2044
2045 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2046 struct net_device *lag)
2047 {
2048 int i, group = -1, err;
2049 struct rtl838x_switch_priv *priv = ds->priv;
2050
2051 mutex_lock(&priv->reg_mutex);
2052 for (i = 0; i < priv->n_lags; i++) {
2053 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2054 group = i;
2055 break;
2056 }
2057 }
2058
2059 if (group == -1) {
2060 pr_info("port_lag_leave: port %d is not a member\n", port);
2061 err = -EINVAL;
2062 goto out;
2063 }
2064
2065 if (port >= priv->cpu_port) {
2066 err = -EINVAL;
2067 goto out;
2068 }
2069 pr_info("port_lag_del: group %d, port %d\n",group, port);
2070 priv->lagmembers &=~ (1ULL << port);
2071 priv->lag_primary[i] = -1;
2072 priv->is_lagmember[port] = 0;
2073 pr_debug("lag_members = %llX\n", priv->lagmembers);
2074 err = rtl83xx_lag_del(priv->ds, group, port);
2075 if (err) {
2076 err = -EINVAL;
2077 goto out;
2078 }
2079 if (!priv->lags_port_members[i])
2080 priv->lag_devs[i] = NULL;
2081
2082 out:
2083 mutex_unlock(&priv->reg_mutex);
2084 return 0;
2085 }
2086
2087 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2088 {
2089 u32 val;
2090 u32 offset = 0;
2091 struct rtl838x_switch_priv *priv = ds->priv;
2092
2093 if ((phy_addr >= 24) &&
2094 (phy_addr <= 27) &&
2095 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2096 if (phy_addr == 26)
2097 offset = 0x100;
2098 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2099 return val;
2100 }
2101
2102 read_phy(phy_addr, 0, phy_reg, &val);
2103 return val;
2104 }
2105
2106 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2107 {
2108 u32 offset = 0;
2109 struct rtl838x_switch_priv *priv = ds->priv;
2110
2111 if ((phy_addr >= 24) &&
2112 (phy_addr <= 27) &&
2113 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2114 if (phy_addr == 26)
2115 offset = 0x100;
2116 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2117 return 0;
2118 }
2119 return write_phy(phy_addr, 0, phy_reg, val);
2120 }
2121
2122 const struct dsa_switch_ops rtl83xx_switch_ops = {
2123 .get_tag_protocol = rtl83xx_get_tag_protocol,
2124 .setup = rtl83xx_setup,
2125
2126 .phy_read = dsa_phy_read,
2127 .phy_write = dsa_phy_write,
2128
2129 .phylink_validate = rtl83xx_phylink_validate,
2130 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2131 .phylink_mac_config = rtl83xx_phylink_mac_config,
2132 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2133 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2134
2135 .get_strings = rtl83xx_get_strings,
2136 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2137 .get_sset_count = rtl83xx_get_sset_count,
2138
2139 .port_enable = rtl83xx_port_enable,
2140 .port_disable = rtl83xx_port_disable,
2141
2142 .get_mac_eee = rtl83xx_get_mac_eee,
2143 .set_mac_eee = rtl83xx_set_mac_eee,
2144
2145 .set_ageing_time = rtl83xx_set_ageing_time,
2146 .port_bridge_join = rtl83xx_port_bridge_join,
2147 .port_bridge_leave = rtl83xx_port_bridge_leave,
2148 .port_stp_state_set = rtl83xx_port_stp_state_set,
2149 .port_fast_age = rtl83xx_fast_age,
2150
2151 .port_vlan_filtering = rtl83xx_vlan_filtering,
2152 .port_vlan_add = rtl83xx_vlan_add,
2153 .port_vlan_del = rtl83xx_vlan_del,
2154
2155 .port_fdb_add = rtl83xx_port_fdb_add,
2156 .port_fdb_del = rtl83xx_port_fdb_del,
2157 .port_fdb_dump = rtl83xx_port_fdb_dump,
2158
2159 .port_mdb_add = rtl83xx_port_mdb_add,
2160 .port_mdb_del = rtl83xx_port_mdb_del,
2161
2162 .port_mirror_add = rtl83xx_port_mirror_add,
2163 .port_mirror_del = rtl83xx_port_mirror_del,
2164
2165 .port_lag_change = rtl83xx_port_lag_change,
2166 .port_lag_join = rtl83xx_port_lag_join,
2167 .port_lag_leave = rtl83xx_port_lag_leave,
2168
2169 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2170 .port_bridge_flags = rtl83xx_port_bridge_flags,
2171 };
2172
2173 const struct dsa_switch_ops rtl930x_switch_ops = {
2174 .get_tag_protocol = rtl83xx_get_tag_protocol,
2175 .setup = rtl93xx_setup,
2176
2177 .phy_read = dsa_phy_read,
2178 .phy_write = dsa_phy_write,
2179
2180 .phylink_validate = rtl93xx_phylink_validate,
2181 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2182 .phylink_mac_config = rtl93xx_phylink_mac_config,
2183 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2184 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2185
2186 .get_strings = rtl83xx_get_strings,
2187 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2188 .get_sset_count = rtl83xx_get_sset_count,
2189
2190 .port_enable = rtl83xx_port_enable,
2191 .port_disable = rtl83xx_port_disable,
2192
2193 .get_mac_eee = rtl93xx_get_mac_eee,
2194 .set_mac_eee = rtl83xx_set_mac_eee,
2195
2196 .set_ageing_time = rtl83xx_set_ageing_time,
2197 .port_bridge_join = rtl83xx_port_bridge_join,
2198 .port_bridge_leave = rtl83xx_port_bridge_leave,
2199 .port_stp_state_set = rtl83xx_port_stp_state_set,
2200 .port_fast_age = rtl930x_fast_age,
2201
2202 .port_vlan_filtering = rtl83xx_vlan_filtering,
2203 .port_vlan_add = rtl83xx_vlan_add,
2204 .port_vlan_del = rtl83xx_vlan_del,
2205
2206 .port_fdb_add = rtl83xx_port_fdb_add,
2207 .port_fdb_del = rtl83xx_port_fdb_del,
2208 .port_fdb_dump = rtl83xx_port_fdb_dump,
2209
2210 .port_mdb_add = rtl83xx_port_mdb_add,
2211 .port_mdb_del = rtl83xx_port_mdb_del,
2212
2213 .port_lag_change = rtl83xx_port_lag_change,
2214 .port_lag_join = rtl83xx_port_lag_join,
2215 .port_lag_leave = rtl83xx_port_lag_leave,
2216
2217 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2218 .port_bridge_flags = rtl83xx_port_bridge_flags,
2219 };
OpenWrt Source Repository