target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Setup for the Realtek RTL838X SoC:
   4  *      Memory, Timer and Serial
   5  *
   6  * Copyright (C) 2020 B. Koblitz
   7  * based on the original BSP by
   8  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   9  *
  10  */
  11
  12 #include <linux/console.h>
  13 #include <linux/init.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/of_fdt.h>
  18
  19 #include <asm/addrspace.h>
  20 #include <asm/io.h>
  21 #include <asm/bootinfo.h>
  22 #include <asm/reboot.h>
  23 #include <asm/time.h>
  24 #include <asm/prom.h>
  25 #include <asm/smp-ops.h>
  26
  27 #include "mach-rtl83xx.h"
  28
  29 extern struct rtl83xx_soc_info soc_info;
  30
  31 u32 pll_reset_value;
  32
  33 static void rtl838x_restart(char *command)
  34 {
  35         u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
  36
  37         pr_info("System restart.\n");
  38         pr_info("PLL control register: %x, applying reset value %x\n",
  39                 pll, pll_reset_value);
  40
  41         sw_w32(3, RTL838X_INT_RW_CTRL);
  42         sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
  43         sw_w32(0, RTL838X_INT_RW_CTRL);
  44
  45         /* Reset Global Control1 Register */
  46         sw_w32(1, RTL838X_RST_GLB_CTRL_1);
  47 }
  48
  49 static void rtl839x_restart(char *command)
  50 {
  51         /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
  52         void (*f)(void) = (void *) 0xbfc00000;
  53
  54         pr_info("System restart.\n");
  55         /* Reset SoC */
  56         sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
  57         /* and call reset vector */
  58         f();
  59         /* If this fails, halt the CPU */
  60         while
  61                 (1);
  62 }
  63
  64 static void rtl930x_restart(char *command)
  65 {
  66         pr_info("System restart.\n");
  67         sw_w32(0x1, RTL930X_RST_GLB_CTRL_0);
  68         while
  69                 (1);
  70 }
  71
  72 static void rtl931x_restart(char *command)
  73 {
  74         u32 v;
  75
  76         pr_info("System restart.\n");
  77         sw_w32(1, RTL931X_RST_GLB_CTRL);
  78         v = sw_r32(RTL931X_RST_GLB_CTRL);
  79         sw_w32(0x101, RTL931X_RST_GLB_CTRL);
  80         msleep(15);
  81         sw_w32(v, RTL931X_RST_GLB_CTRL);
  82         msleep(15);
  83         sw_w32(0x101, RTL931X_RST_GLB_CTRL);
  84 }
  85
  86 static void rtl838x_halt(void)
  87 {
  88         pr_info("System halted.\n");
  89         while
  90                 (1);
  91 }
  92
  93 static void __init rtl838x_setup(void)
  94 {
  95         pr_info("Registering _machine_restart\n");
  96         _machine_restart = rtl838x_restart;
  97         _machine_halt = rtl838x_halt;
  98
  99         /* This PLL value needs to be restored before a reset and will then be
 100          * preserved over a SoC reset. A wrong value prevents the SoC from
 101          * connecting to the SPI flash controller at boot and reading the
 102          * reset routine */
 103         pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
 104
 105         /* Setup System LED. Bit 15 then allows to toggle it */
 106         sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
 107 }
 108
 109 static void __init rtl839x_setup(void)
 110 {
 111         pr_info("Registering _machine_restart\n");
 112         _machine_restart = rtl839x_restart;
 113         _machine_halt = rtl838x_halt;
 114
 115         /* Setup System LED. Bit 14 of RTL839X_LED_GLB_CTRL then allows to toggle it */
 116         sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
 117 }
 118
 119 static void __init rtl930x_setup(void)
 120 {
 121         pr_info("Registering _machine_restart\n");
 122         _machine_restart = rtl930x_restart;
 123         _machine_halt = rtl838x_halt;
 124
 125         if (soc_info.id == 0x9302)
 126                 sw_w32_mask(0, 3 << 13, RTL9302_LED_GLB_CTRL);
 127         else
 128                 sw_w32_mask(0, 3 << 13, RTL930X_LED_GLB_CTRL);
 129 }
 130
 131 static void __init rtl931x_setup(void)
 132 {
 133         pr_info("Registering _machine_restart\n");
 134         _machine_restart = rtl931x_restart;
 135         _machine_halt = rtl838x_halt;
 136         sw_w32_mask(0, 3 << 12, RTL931X_LED_GLB_CTRL);
 137 }
 138
 139 void __init plat_mem_setup(void)
 140 {
 141         void *dtb;
 142
 143         set_io_port_base(KSEG1);
 144         _machine_restart = rtl838x_restart;
 145
 146         if (fw_passed_dtb) /* UHI interface */
 147                 dtb = (void *)fw_passed_dtb;
 148         else if (__dtb_start != __dtb_end)
 149                 dtb = (void *)__dtb_start;
 150         else
 151                 panic("no dtb found");
 152
 153         /*
 154          * Load the devicetree. This causes the chosen node to be
 155          * parsed resulting in our memory appearing
 156          */
 157         __dt_setup_arch(dtb);
 158
 159         switch (soc_info.family) {
 160         case RTL8380_FAMILY_ID:
 161                 rtl838x_setup();
 162                 break;
 163         case RTL8390_FAMILY_ID:
 164                 rtl839x_setup();
 165                 break;
 166         case RTL9300_FAMILY_ID:
 167                 rtl930x_setup();
 168                 break;
 169         case RTL9310_FAMILY_ID:
 170                 rtl931x_setup();
 171                 break;
 172         }
 173 }
 174
 175 void __init plat_time_init(void)
 176 {
 177         struct device_node *np;
 178         u32 freq = 500000000;
 179
 180         of_clk_init(NULL);
 181         timer_probe();
 182
 183         np = of_find_node_by_name(NULL, "cpus");
 184         if (!np) {
 185                 pr_err("Missing 'cpus' DT node, using default frequency.");
 186         } else {
 187                 if (of_property_read_u32(np, "frequency", &freq) < 0)
 188                         pr_err("No 'frequency' property in DT, using default.");
 189                 else
 190                         pr_info("CPU frequency from device tree: %dMHz", freq / 1000000);
 191                 of_node_put(np);
 192         }
 193
 194         mips_hpt_frequency = freq / 2;
 195 }