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base-files: Make sure rootfs_data_max is considered
[openwrt/openwrt.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / common.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 extern const struct rtl838x_reg rtl838x_reg;
12 extern const struct rtl838x_reg rtl839x_reg;
13 extern const struct rtl838x_reg rtl930x_reg;
14 extern const struct rtl838x_reg rtl931x_reg;
15
16 extern const struct dsa_switch_ops rtl83xx_switch_ops;
17 extern const struct dsa_switch_ops rtl930x_switch_ops;
18
19 DEFINE_MUTEX(smi_lock);
20
21 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
22 {
23 u32 msti = 0;
24 u32 port_state[4];
25 int index, bit;
26 int pos = port;
27 int n = priv->port_width << 1;
28
29 /* Ports above or equal CPU port can never be configured */
30 if (port >= priv->cpu_port)
31 return -1;
32
33 mutex_lock(&priv->reg_mutex);
34
35 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
36 if (priv->family_id == RTL8390_FAMILY_ID)
37 pos += 12;
38 if (priv->family_id == RTL9300_FAMILY_ID)
39 pos += 3;
40 if (priv->family_id == RTL9310_FAMILY_ID)
41 pos += 8;
42
43 index = n - (pos >> 4) - 1;
44 bit = (pos << 1) % 32;
45
46 priv->r->stp_get(priv, msti, port_state);
47
48 mutex_unlock(&priv->reg_mutex);
49
50 return (port_state[index] >> bit) & 3;
51 }
52
53 static struct table_reg rtl838x_tbl_regs[] = {
54 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
55 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
56 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
57
58 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
59 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
60 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
61 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
62
63 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
64 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
65 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
66 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
67 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
68 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
69
70 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
71 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
72 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
73 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
74 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
75 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
76 };
77
78 void rtl_table_init(void)
79 {
80 int i;
81
82 for (i = 0; i < RTL_TBL_END; i++)
83 mutex_init(&rtl838x_tbl_regs[i].lock);
84 }
85
86 /*
87 * Request access to table t in table access register r
88 * Returns a handle to a lock for that table
89 */
90 struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
91 {
92 if (r >= RTL_TBL_END)
93 return NULL;
94
95 if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
96 return NULL;
97
98 mutex_lock(&rtl838x_tbl_regs[r].lock);
99 rtl838x_tbl_regs[r].tbl = t;
100
101 return &rtl838x_tbl_regs[r];
102 }
103
104 /*
105 * Release a table r, unlock the corresponding lock
106 */
107 void rtl_table_release(struct table_reg *r)
108 {
109 if (!r)
110 return;
111
112 // pr_info("Unlocking %08x\n", (u32)r);
113 mutex_unlock(&r->lock);
114 // pr_info("Unlock done\n");
115 }
116
117 /*
118 * Reads table index idx into the data registers of the table
119 */
120 void rtl_table_read(struct table_reg *r, int idx)
121 {
122 u32 cmd = r->rmode ? BIT(r->c_bit) : 0;
123
124 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
125 sw_w32(cmd, r->addr);
126 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
127 }
128
129 /*
130 * Writes the content of the table data registers into the table at index idx
131 */
132 void rtl_table_write(struct table_reg *r, int idx)
133 {
134 u32 cmd = r->rmode ? 0 : BIT(r->c_bit);
135
136 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
137 sw_w32(cmd, r->addr);
138 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
139 }
140
141 /*
142 * Returns the address of the ith data register of table register r
143 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
144 */
145 inline u16 rtl_table_data(struct table_reg *r, int i)
146 {
147 if (i >= r->max_data)
148 i = r->max_data - 1;
149 return r->data + i * 4;
150 }
151
152 inline u32 rtl_table_data_r(struct table_reg *r, int i)
153 {
154 return sw_r32(rtl_table_data(r, i));
155 }
156
157 inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
158 {
159 sw_w32(v, rtl_table_data(r, i));
160 }
161
162 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
163 void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
164 {
165 sw_w32_mask((u32)clear, (u32)set, reg);
166 }
167
168 void rtl838x_set_port_reg(u64 set, int reg)
169 {
170 sw_w32((u32)set, reg);
171 }
172
173 u64 rtl838x_get_port_reg(int reg)
174 {
175 return ((u64) sw_r32(reg));
176 }
177
178 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
179 void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
180 {
181 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
182 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
183 }
184
185 u64 rtl839x_get_port_reg_be(int reg)
186 {
187 u64 v = sw_r32(reg);
188
189 v <<= 32;
190 v |= sw_r32(reg + 4);
191 return v;
192 }
193
194 void rtl839x_set_port_reg_be(u64 set, int reg)
195 {
196 sw_w32(set >> 32, reg);
197 sw_w32(set & 0xffffffff, reg + 4);
198 }
199
200 void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
201 {
202 sw_w32_mask((u32)clear, (u32)set, reg);
203 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
204 }
205
206 void rtl839x_set_port_reg_le(u64 set, int reg)
207 {
208 sw_w32(set, reg);
209 sw_w32(set >> 32, reg + 4);
210 }
211
212 u64 rtl839x_get_port_reg_le(int reg)
213 {
214 u64 v = sw_r32(reg + 4);
215
216 v <<= 32;
217 v |= sw_r32(reg);
218 return v;
219 }
220
221 int read_phy(u32 port, u32 page, u32 reg, u32 *val)
222 {
223 switch (soc_info.family) {
224 case RTL8380_FAMILY_ID:
225 return rtl838x_read_phy(port, page, reg, val);
226 case RTL8390_FAMILY_ID:
227 return rtl839x_read_phy(port, page, reg, val);
228 case RTL9300_FAMILY_ID:
229 return rtl930x_read_phy(port, page, reg, val);
230 case RTL9310_FAMILY_ID:
231 return rtl931x_read_phy(port, page, reg, val);
232 }
233 return -1;
234 }
235
236 int write_phy(u32 port, u32 page, u32 reg, u32 val)
237 {
238 switch (soc_info.family) {
239 case RTL8380_FAMILY_ID:
240 return rtl838x_write_phy(port, page, reg, val);
241 case RTL8390_FAMILY_ID:
242 return rtl839x_write_phy(port, page, reg, val);
243 case RTL9300_FAMILY_ID:
244 return rtl930x_write_phy(port, page, reg, val);
245 case RTL9310_FAMILY_ID:
246 return rtl931x_write_phy(port, page, reg, val);
247 }
248 return -1;
249 }
250
251 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
252 {
253 struct device *dev = priv->dev;
254 struct device_node *dn, *mii_np = dev->of_node;
255 struct mii_bus *bus;
256 int ret;
257 u32 pn;
258
259 pr_debug("In %s\n", __func__);
260 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
261 if (mii_np) {
262 pr_debug("Found compatible MDIO node!\n");
263 } else {
264 dev_err(priv->dev, "no %s child node found", "mdio-bus");
265 return -ENODEV;
266 }
267
268 priv->mii_bus = of_mdio_find_bus(mii_np);
269 if (!priv->mii_bus) {
270 pr_debug("Deferring probe of mdio bus\n");
271 return -EPROBE_DEFER;
272 }
273 if (!of_device_is_available(mii_np))
274 ret = -ENODEV;
275
276 bus = devm_mdiobus_alloc(priv->ds->dev);
277 if (!bus)
278 return -ENOMEM;
279
280 bus->name = "rtl838x slave mii";
281
282 /*
283 * Since the NIC driver is loaded first, we can use the mdio rw functions
284 * assigned there.
285 */
286 bus->read = priv->mii_bus->read;
287 bus->write = priv->mii_bus->write;
288 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
289
290 bus->parent = dev;
291 priv->ds->slave_mii_bus = bus;
292 priv->ds->slave_mii_bus->priv = priv;
293
294 ret = mdiobus_register(priv->ds->slave_mii_bus);
295 if (ret && mii_np) {
296 of_node_put(dn);
297 return ret;
298 }
299
300 dn = mii_np;
301 for_each_node_by_name(dn, "ethernet-phy") {
302 if (of_property_read_u32(dn, "reg", &pn))
303 continue;
304
305 priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
306
307 // Check for the integrated SerDes of the RTL8380M first
308 if (of_property_read_bool(dn, "phy-is-integrated")
309 && priv->id == 0x8380 && pn >= 24) {
310 pr_debug("----> FÓUND A SERDES\n");
311 priv->ports[pn].phy = PHY_RTL838X_SDS;
312 continue;
313 }
314
315 if (of_property_read_bool(dn, "phy-is-integrated")
316 && !of_property_read_bool(dn, "sfp")) {
317 priv->ports[pn].phy = PHY_RTL8218B_INT;
318 continue;
319 }
320
321 if (!of_property_read_bool(dn, "phy-is-integrated")
322 && of_property_read_bool(dn, "sfp")) {
323 priv->ports[pn].phy = PHY_RTL8214FC;
324 continue;
325 }
326
327 if (!of_property_read_bool(dn, "phy-is-integrated")
328 && !of_property_read_bool(dn, "sfp")) {
329 priv->ports[pn].phy = PHY_RTL8218B_EXT;
330 continue;
331 }
332 }
333
334 // TODO: Do this needs to come from the .dts, at least the SerDes number
335 if (priv->family_id == RTL9300_FAMILY_ID) {
336 priv->ports[24].is2G5 = true;
337 priv->ports[25].is2G5 = true;
338 priv->ports[24].sds_num = 1;
339 priv->ports[24].sds_num = 2;
340 }
341
342 /* Disable MAC polling the PHY so that we can start configuration */
343 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
344
345 /* Enable PHY control via SoC */
346 if (priv->family_id == RTL8380_FAMILY_ID) {
347 /* Enable SerDes NWAY and PHY control via SoC */
348 sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
349 } else {
350 /* Disable PHY polling via SoC */
351 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
352 }
353
354 /* Power on fibre ports and reset them if necessary */
355 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
356 pr_debug("Powering on fibre ports & reset\n");
357 rtl8380_sds_power(24, 1);
358 rtl8380_sds_power(26, 1);
359 }
360
361 // TODO: Only power on SerDes with external PHYs connected
362 if (priv->family_id == RTL9300_FAMILY_ID) {
363 pr_info("RTL9300 Powering on SerDes ports\n");
364 rtl9300_sds_power(24, 1);
365 rtl9300_sds_power(25, 1);
366 rtl9300_sds_power(26, 1);
367 rtl9300_sds_power(27, 1);
368 }
369
370 pr_debug("%s done\n", __func__);
371 return 0;
372 }
373
374 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
375 {
376 int t = sw_r32(priv->r->l2_ctrl_1);
377
378 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
379
380 if (priv->family_id == RTL8380_FAMILY_ID)
381 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
382 else
383 t = (t * 3) / 5;
384
385 pr_debug("L2 AGING time: %d sec\n", t);
386 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
387 return t;
388 }
389
390 /* Caller must hold priv->reg_mutex */
391 int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port)
392 {
393 struct rtl838x_switch_priv *priv = ds->priv;
394 int i;
395
396 pr_info("%s: Adding port %d to LA-group %d\n", __func__, port, group);
397 if (group >= priv->n_lags) {
398 pr_err("Link Agrregation group too large.\n");
399 return -EINVAL;
400 }
401
402 if (port >= priv->cpu_port) {
403 pr_err("Invalid port number.\n");
404 return -EINVAL;
405 }
406
407 for (i = 0; i < priv->n_lags; i++) {
408 if (priv->lags_port_members[i] & BIT_ULL(i))
409 break;
410 }
411 if (i != priv->n_lags) {
412 pr_err("%s: Port already member of LAG: %d\n", __func__, i);
413 return -ENOSPC;
414 }
415
416 priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
417 priv->lags_port_members[group] |= BIT_ULL(port);
418
419 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
420 return 0;
421 }
422
423 /* Caller must hold priv->reg_mutex */
424 int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
425 {
426 struct rtl838x_switch_priv *priv = ds->priv;
427
428 pr_info("%s: Removing port %d from LA-group %d\n", __func__, port, group);
429
430 if (group >= priv->n_lags) {
431 pr_err("Link Agrregation group too large.\n");
432 return -EINVAL;
433 }
434
435 if (port >= priv->cpu_port) {
436 pr_err("Invalid port number.\n");
437 return -EINVAL;
438 }
439
440
441 if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
442 pr_err("%s: Port not member of LAG: %d\n", __func__, group
443 );
444 return -ENOSPC;
445 }
446
447 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
448 priv->lags_port_members[group] &= ~BIT_ULL(port);
449
450 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
451 return 0;
452 }
453
454 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
455 struct net_device *ndev,
456 struct netdev_notifier_changeupper_info *info)
457 {
458 struct net_device *upper = info->upper_dev;
459 int i, j, err;
460
461 if (!netif_is_lag_master(upper))
462 return 0;
463
464 mutex_lock(&priv->reg_mutex);
465
466 for (i = 0; i < priv->n_lags; i++) {
467 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
468 break;
469 }
470 for (j = 0; j < priv->cpu_port; j++) {
471 if (priv->ports[j].dp->slave == ndev)
472 break;
473 }
474 if (j >= priv->cpu_port) {
475 err = -EINVAL;
476 goto out;
477 }
478
479 if (info->linking) {
480 if (!priv->lag_devs[i])
481 priv->lag_devs[i] = upper;
482 err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index);
483 if (err) {
484 err = -EINVAL;
485 goto out;
486 }
487 } else {
488 if (!priv->lag_devs[i])
489 err = -EINVAL;
490 err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
491 if (err) {
492 err = -EINVAL;
493 goto out;
494 }
495 if (!priv->lags_port_members[i])
496 priv->lag_devs[i] = NULL;
497 }
498
499 out:
500 mutex_unlock(&priv->reg_mutex);
501 return 0;
502 }
503
504 static int rtl83xx_netdevice_event(struct notifier_block *this,
505 unsigned long event, void *ptr)
506 {
507 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
508 struct rtl838x_switch_priv *priv;
509 int err;
510
511 pr_debug("In: %s, event: %lu\n", __func__, event);
512
513 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
514 return NOTIFY_DONE;
515
516 priv = container_of(this, struct rtl838x_switch_priv, nb);
517 switch (event) {
518 case NETDEV_CHANGEUPPER:
519 err = rtl83xx_handle_changeupper(priv, ndev, ptr);
520 break;
521 }
522
523 if (err)
524 return err;
525
526 return NOTIFY_DONE;
527 }
528
529 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
530 {
531 int err = 0, i;
532 struct rtl838x_switch_priv *priv;
533 struct device *dev = &pdev->dev;
534 u64 bpdu_mask;
535
536 pr_debug("Probing RTL838X switch device\n");
537 if (!pdev->dev.of_node) {
538 dev_err(dev, "No DT found\n");
539 return -EINVAL;
540 }
541
542 // Initialize access to RTL switch tables
543 rtl_table_init();
544
545 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
546 if (!priv)
547 return -ENOMEM;
548
549 priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
550
551 if (!priv->ds)
552 return -ENOMEM;
553 priv->ds->dev = dev;
554 priv->ds->priv = priv;
555 priv->ds->ops = &rtl83xx_switch_ops;
556 priv->dev = dev;
557
558 priv->family_id = soc_info.family;
559 priv->id = soc_info.id;
560 switch(soc_info.family) {
561 case RTL8380_FAMILY_ID:
562 priv->ds->ops = &rtl83xx_switch_ops;
563 priv->cpu_port = RTL838X_CPU_PORT;
564 priv->port_mask = 0x1f;
565 priv->port_width = 1;
566 priv->irq_mask = 0x0FFFFFFF;
567 priv->r = &rtl838x_reg;
568 priv->ds->num_ports = 29;
569 priv->fib_entries = 8192;
570 rtl8380_get_version(priv);
571 priv->n_lags = 8;
572 priv->l2_bucket_size = 4;
573 break;
574 case RTL8390_FAMILY_ID:
575 priv->ds->ops = &rtl83xx_switch_ops;
576 priv->cpu_port = RTL839X_CPU_PORT;
577 priv->port_mask = 0x3f;
578 priv->port_width = 2;
579 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
580 priv->r = &rtl839x_reg;
581 priv->ds->num_ports = 53;
582 priv->fib_entries = 16384;
583 rtl8390_get_version(priv);
584 priv->n_lags = 16;
585 priv->l2_bucket_size = 4;
586 break;
587 case RTL9300_FAMILY_ID:
588 priv->ds->ops = &rtl930x_switch_ops;
589 priv->cpu_port = RTL930X_CPU_PORT;
590 priv->port_mask = 0x1f;
591 priv->port_width = 1;
592 priv->irq_mask = 0x0FFFFFFF;
593 priv->r = &rtl930x_reg;
594 priv->ds->num_ports = 29;
595 priv->fib_entries = 16384;
596 priv->version = RTL8390_VERSION_A;
597 priv->n_lags = 16;
598 sw_w32(1, RTL930X_ST_CTRL);
599 priv->l2_bucket_size = 8;
600 break;
601 case RTL9310_FAMILY_ID:
602 priv->ds->ops = &rtl930x_switch_ops;
603 priv->cpu_port = RTL931X_CPU_PORT;
604 priv->port_mask = 0x3f;
605 priv->port_width = 2;
606 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
607 priv->r = &rtl931x_reg;
608 priv->ds->num_ports = 57;
609 priv->fib_entries = 16384;
610 priv->version = RTL8390_VERSION_A;
611 priv->n_lags = 16;
612 priv->l2_bucket_size = 8;
613 break;
614 }
615 pr_debug("Chip version %c\n", priv->version);
616
617 err = rtl83xx_mdio_probe(priv);
618 if (err) {
619 /* Probing fails the 1st time because of missing ethernet driver
620 * initialization. Use this to disable traffic in case the bootloader left if on
621 */
622 return err;
623 }
624 err = dsa_register_switch(priv->ds);
625 if (err) {
626 dev_err(dev, "Error registering switch: %d\n", err);
627 return err;
628 }
629
630 /* Enable link and media change interrupts. Are the SERDES masks needed? */
631 sw_w32_mask(0, 3, priv->r->isr_glb_src);
632
633 priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
634 priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
635
636 priv->link_state_irq = platform_get_irq(pdev, 0);
637 pr_info("LINK state irq: %d\n", priv->link_state_irq);
638 switch (priv->family_id) {
639 case RTL8380_FAMILY_ID:
640 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
641 IRQF_SHARED, "rtl838x-link-state", priv->ds);
642 break;
643 case RTL8390_FAMILY_ID:
644 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
645 IRQF_SHARED, "rtl839x-link-state", priv->ds);
646 break;
647 case RTL9300_FAMILY_ID:
648 err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
649 IRQF_SHARED, "rtl930x-link-state", priv->ds);
650 break;
651 case RTL9310_FAMILY_ID:
652 err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
653 IRQF_SHARED, "rtl931x-link-state", priv->ds);
654 break;
655 }
656 if (err) {
657 dev_err(dev, "Error setting up switch interrupt.\n");
658 /* Need to free allocated switch here */
659 }
660
661 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
662 if (soc_info.family != RTL9310_FAMILY_ID)
663 sw_w32(0x1, priv->r->imr_glb);
664
665 rtl83xx_get_l2aging(priv);
666
667 rtl83xx_setup_qos(priv);
668
669 /* Clear all destination ports for mirror groups */
670 for (i = 0; i < 4; i++)
671 priv->mirror_group_ports[i] = -1;
672
673 priv->nb.notifier_call = rtl83xx_netdevice_event;
674 if (register_netdevice_notifier(&priv->nb)) {
675 priv->nb.notifier_call = NULL;
676 dev_err(dev, "Failed to register LAG netdev notifier\n");
677 }
678
679 // Flood BPDUs to all ports including cpu-port
680 if (soc_info.family != RTL9300_FAMILY_ID) { // TODO: Port this functionality
681 bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
682 priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
683
684 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
685 sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
686
687 rtl838x_dbgfs_init(priv);
688 }
689
690 return err;
691 }
692
693 static int rtl83xx_sw_remove(struct platform_device *pdev)
694 {
695 // TODO:
696 pr_debug("Removing platform driver for rtl83xx-sw\n");
697 return 0;
698 }
699
700 static const struct of_device_id rtl83xx_switch_of_ids[] = {
701 { .compatible = "realtek,rtl83xx-switch"},
702 { /* sentinel */ }
703 };
704
705
706 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
707
708 static struct platform_driver rtl83xx_switch_driver = {
709 .probe = rtl83xx_sw_probe,
710 .remove = rtl83xx_sw_remove,
711 .driver = {
712 .name = "rtl83xx-switch",
713 .pm = NULL,
714 .of_match_table = rtl83xx_switch_of_ids,
715 },
716 };
717
718 module_platform_driver(rtl83xx_switch_driver);
719
720 MODULE_AUTHOR("B. Koblitz");
721 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
722 MODULE_LICENSE("GPL");
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