1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
10 extern struct rtl83xx_soc_info soc_info
;
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv
*priv
)
15 mutex_lock(&priv
->reg_mutex
);
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
20 if (priv
->family_id
== RTL8380_FAMILY_ID
)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL
);
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv
->r
->stat_rst
);
26 mutex_unlock(&priv
->reg_mutex
);
29 static void rtl83xx_write_cam(int idx
, u32
*r
)
31 u32 cmd
= BIT(16) /* Execute cmd */
33 | BIT(13) /* Table type 0b01 */
36 sw_w32(r
[0], RTL838X_TBL_ACCESS_L2_DATA(0));
37 sw_w32(r
[1], RTL838X_TBL_ACCESS_L2_DATA(1));
38 sw_w32(r
[2], RTL838X_TBL_ACCESS_L2_DATA(2));
40 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
41 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
44 static u64
rtl83xx_hash_key(struct rtl838x_switch_priv
*priv
, u64 mac
, u32 vid
)
46 switch (priv
->family_id
) {
47 case RTL8380_FAMILY_ID
:
48 return rtl838x_hash(priv
, mac
<< 12 | vid
);
49 case RTL8390_FAMILY_ID
:
50 return rtl839x_hash(priv
, mac
<< 12 | vid
);
51 case RTL9300_FAMILY_ID
:
52 return rtl930x_hash(priv
, ((u64
)vid
) << 48 | mac
);
54 pr_err("Hash not implemented\n");
59 static void rtl83xx_write_hash(int idx
, u32
*r
)
61 u32 cmd
= BIT(16) /* Execute cmd */
63 | 0 << 13 /* Table type 0b00 */
66 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
67 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
68 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
69 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
70 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
73 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv
*priv
)
79 /* Enable all ports with a PHY, including the SFP-ports */
80 for (i
= 0; i
< priv
->cpu_port
; i
++) {
81 if (priv
->ports
[i
].phy
)
85 pr_debug("%s: %16llx\n", __func__
, v
);
86 priv
->r
->set_port_reg_le(v
, priv
->r
->smi_poll_ctrl
);
88 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
89 if (priv
->family_id
== RTL8390_FAMILY_ID
)
90 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL
);
91 else if(priv
->family_id
== RTL9300_FAMILY_ID
)
92 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL
);
95 const struct rtl83xx_mib_desc rtl83xx_mib
[] = {
96 MIB_DESC(2, 0xf8, "ifInOctets"),
97 MIB_DESC(2, 0xf0, "ifOutOctets"),
98 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
99 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
100 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
101 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
102 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
103 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
104 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
105 MIB_DESC(1, 0xd0, "ifOutDiscards"),
106 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
107 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
108 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
109 MIB_DESC(1, 0xc0, ".3LateCollisions"),
110 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
111 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
112 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
113 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
114 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
115 MIB_DESC(1, 0xa8, "DropEvents"),
116 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
117 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
118 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
119 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
120 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
121 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
122 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
123 MIB_DESC(1, 0x88, "rx_OversizePkts"),
124 MIB_DESC(1, 0x84, "Fragments"),
125 MIB_DESC(1, 0x80, "Jabbers"),
126 MIB_DESC(1, 0x7c, "Collisions"),
127 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
128 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
129 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
130 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
131 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
132 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
133 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
134 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
135 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
136 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
137 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
138 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
139 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
140 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
141 MIB_DESC(1, 0x40, "rxMacDiscards")
148 static enum dsa_tag_protocol
rtl83xx_get_tag_protocol(struct dsa_switch
*ds
, int port
)
150 /* The switch does not tag the frames, instead internally the header
151 * structure for each packet is tagged accordingly.
153 return DSA_TAG_PROTO_TRAILER
;
156 static int rtl83xx_setup(struct dsa_switch
*ds
)
159 struct rtl838x_switch_priv
*priv
= ds
->priv
;
160 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
);
162 pr_debug("%s called\n", __func__
);
164 /* Disable MAC polling the PHY so that we can start configuration */
165 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
167 for (i
= 0; i
< ds
->num_ports
; i
++)
168 priv
->ports
[i
].enable
= false;
169 priv
->ports
[priv
->cpu_port
].enable
= true;
171 /* Isolate ports from each other: traffic only CPU <-> port */
172 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
173 * traffic from source port i to destination port j
175 for (i
= 0; i
< priv
->cpu_port
; i
++) {
176 if (priv
->ports
[i
].phy
) {
177 priv
->r
->set_port_reg_be(BIT_ULL(priv
->cpu_port
) | BIT(i
),
178 priv
->r
->port_iso_ctrl(i
));
179 port_bitmap
|= BIT_ULL(i
);
182 priv
->r
->set_port_reg_be(port_bitmap
, priv
->r
->port_iso_ctrl(priv
->cpu_port
));
184 if (priv
->family_id
== RTL8380_FAMILY_ID
)
185 rtl838x_print_matrix();
187 rtl839x_print_matrix();
189 rtl83xx_init_stats(priv
);
191 ds
->configure_vlan_while_not_filtering
= true;
193 /* Enable MAC Polling PHY again */
194 rtl83xx_enable_phy_polling(priv
);
195 pr_debug("Please wait until PHY is settled\n");
200 static int rtl930x_setup(struct dsa_switch
*ds
)
203 struct rtl838x_switch_priv
*priv
= ds
->priv
;
204 u32 port_bitmap
= BIT(priv
->cpu_port
);
206 pr_info("%s called\n", __func__
);
208 // Enable CSTI STP mode
209 // sw_w32(1, RTL930X_ST_CTRL);
211 /* Disable MAC polling the PHY so that we can start configuration */
212 sw_w32(0, RTL930X_SMI_POLL_CTRL
);
214 // Disable all ports except CPU port
215 for (i
= 0; i
< ds
->num_ports
; i
++)
216 priv
->ports
[i
].enable
= false;
217 priv
->ports
[priv
->cpu_port
].enable
= true;
219 for (i
= 0; i
< priv
->cpu_port
; i
++) {
220 if (priv
->ports
[i
].phy
) {
221 priv
->r
->traffic_set(i
, BIT(priv
->cpu_port
) | BIT(i
));
222 port_bitmap
|= 1ULL << i
;
225 priv
->r
->traffic_set(priv
->cpu_port
, port_bitmap
);
227 rtl930x_print_matrix();
229 // TODO: Initialize statistics
231 ds
->configure_vlan_while_not_filtering
= true;
233 rtl83xx_enable_phy_polling(priv
);
238 static void rtl83xx_phylink_validate(struct dsa_switch
*ds
, int port
,
239 unsigned long *supported
,
240 struct phylink_link_state
*state
)
242 struct rtl838x_switch_priv
*priv
= ds
->priv
;
243 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
245 pr_debug("In %s port %d", __func__
, port
);
247 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
248 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
249 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
250 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
251 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
252 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
253 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
254 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
255 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
256 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
258 "Unsupported interface: %d for port %d\n",
259 state
->interface
, port
);
263 /* Allow all the expected bits */
264 phylink_set(mask
, Autoneg
);
265 phylink_set_port_modes(mask
);
266 phylink_set(mask
, Pause
);
267 phylink_set(mask
, Asym_Pause
);
269 /* With the exclusion of MII and Reverse MII, we support Gigabit,
270 * including Half duplex
272 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
273 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
274 phylink_set(mask
, 1000baseT_Full
);
275 phylink_set(mask
, 1000baseT_Half
);
278 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
279 if (port
>= 24 && port
<= 27 && priv
->family_id
== RTL8380_FAMILY_ID
)
280 phylink_set(mask
, 1000baseX_Full
);
282 phylink_set(mask
, 10baseT_Half
);
283 phylink_set(mask
, 10baseT_Full
);
284 phylink_set(mask
, 100baseT_Half
);
285 phylink_set(mask
, 100baseT_Full
);
287 bitmap_and(supported
, supported
, mask
,
288 __ETHTOOL_LINK_MODE_MASK_NBITS
);
289 bitmap_and(state
->advertising
, state
->advertising
, mask
,
290 __ETHTOOL_LINK_MODE_MASK_NBITS
);
293 static int rtl83xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
294 struct phylink_link_state
*state
)
296 struct rtl838x_switch_priv
*priv
= ds
->priv
;
300 if (port
< 0 || port
> priv
->cpu_port
)
304 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
305 * state needs to be read twice in order to read a correct result.
306 * This would not be necessary for ports connected e.g. to RTL8218D
310 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
311 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
312 if (link
& BIT_ULL(port
))
314 pr_debug("%s: link state: %llx\n", __func__
, link
& BIT_ULL(port
));
317 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
320 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
321 speed
>>= (port
% 16) << 1;
322 switch (speed
& 0x3) {
324 state
->speed
= SPEED_10
;
327 state
->speed
= SPEED_100
;
330 state
->speed
= SPEED_1000
;
333 if (port
== 24 || port
== 26) /* Internal serdes */
334 state
->speed
= SPEED_2500
;
336 state
->speed
= SPEED_100
; /* Is in fact 500Mbit */
339 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
340 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
341 state
->pause
|= MLO_PAUSE_RX
;
342 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
343 state
->pause
|= MLO_PAUSE_TX
;
348 static void rtl83xx_config_interface(int port
, phy_interface_t interface
)
350 u32 old
, int_shift
, sds_shift
;
365 old
= sw_r32(RTL838X_SDS_MODE_SEL
);
367 case PHY_INTERFACE_MODE_1000BASEX
:
368 if ((old
>> sds_shift
& 0x1f) == 4)
370 sw_w32_mask(0x7 << int_shift
, 1 << int_shift
, RTL838X_INT_MODE_CTRL
);
371 sw_w32_mask(0x1f << sds_shift
, 4 << sds_shift
, RTL838X_SDS_MODE_SEL
);
373 case PHY_INTERFACE_MODE_SGMII
:
374 if ((old
>> sds_shift
& 0x1f) == 2)
376 sw_w32_mask(0x7 << int_shift
, 2 << int_shift
, RTL838X_INT_MODE_CTRL
);
377 sw_w32_mask(0x1f << sds_shift
, 2 << sds_shift
, RTL838X_SDS_MODE_SEL
);
382 pr_debug("configured port %d for interface %s\n", port
, phy_modes(interface
));
385 static void rtl83xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
387 const struct phylink_link_state
*state
)
389 struct rtl838x_switch_priv
*priv
= ds
->priv
;
391 int speed_bit
= priv
->family_id
== RTL8380_FAMILY_ID
? 4 : 3;
393 pr_debug("%s port %d, mode %x\n", __func__
, port
, mode
);
395 // BUG: Make this work on RTL93XX
396 if (priv
->family_id
>= RTL9300_FAMILY_ID
)
399 if (port
== priv
->cpu_port
) {
400 /* Set Speed, duplex, flow control
401 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
402 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
405 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
406 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
407 /* allow CRC errors on CPU-port */
408 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv
->cpu_port
));
410 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
415 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
416 /* Auto-Negotiation does not work for MAC in RTL8390 */
417 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
418 if (mode
== MLO_AN_PHY
|| phylink_autoneg_inband(mode
)) {
419 pr_debug("PHY autonegotiates\n");
421 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
422 rtl83xx_config_interface(port
, state
->interface
);
427 if (mode
!= MLO_AN_FIXED
)
428 pr_debug("Fixed state.\n");
430 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
431 /* Clear id_mode_dis bit, and the existing port mode, let
432 * RGMII_MODE_EN bet set by mac_link_{up,down}
434 reg
&= ~(RX_PAUSE_EN
| TX_PAUSE_EN
);
436 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
437 if (state
->pause
& MLO_PAUSE_TX
)
443 reg
&= ~(3 << speed_bit
);
444 switch (state
->speed
) {
446 reg
|= 2 << speed_bit
;
449 reg
|= 1 << speed_bit
;
453 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
454 reg
&= ~(DUPLEX_FULL
| FORCE_LINK_EN
);
456 reg
|= FORCE_LINK_EN
;
457 if (state
->duplex
== DUPLEX_FULL
)
462 if (priv
->family_id
== RTL8380_FAMILY_ID
)
464 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
467 static void rtl83xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
469 phy_interface_t interface
)
471 struct rtl838x_switch_priv
*priv
= ds
->priv
;
472 /* Stop TX/RX to port */
473 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
476 static void rtl83xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
478 phy_interface_t interface
,
479 struct phy_device
*phydev
)
481 struct rtl838x_switch_priv
*priv
= ds
->priv
;
482 /* Restart TX/RX to port */
483 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
486 static void rtl83xx_get_strings(struct dsa_switch
*ds
,
487 int port
, u32 stringset
, u8
*data
)
491 if (stringset
!= ETH_SS_STATS
)
494 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++)
495 strncpy(data
+ i
* ETH_GSTRING_LEN
, rtl83xx_mib
[i
].name
,
499 static void rtl83xx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
502 struct rtl838x_switch_priv
*priv
= ds
->priv
;
503 const struct rtl83xx_mib_desc
*mib
;
507 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++) {
508 mib
= &rtl83xx_mib
[i
];
510 data
[i
] = sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 252 - mib
->offset
);
511 if (mib
->size
== 2) {
512 h
= sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 248 - mib
->offset
);
518 static int rtl83xx_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
520 if (sset
!= ETH_SS_STATS
)
523 return ARRAY_SIZE(rtl83xx_mib
);
526 static int rtl83xx_port_enable(struct dsa_switch
*ds
, int port
,
527 struct phy_device
*phydev
)
529 struct rtl838x_switch_priv
*priv
= ds
->priv
;
532 pr_debug("%s: %x %d", __func__
, (u32
) priv
, port
);
533 priv
->ports
[port
].enable
= true;
535 /* enable inner tagging on egress, do not keep any tags */
536 if (priv
->family_id
== RTL9310_FAMILY_ID
)
537 sw_w32(BIT(4), priv
->r
->vlan_port_tag_sts_ctrl
+ (port
<< 2));
539 sw_w32(1, priv
->r
->vlan_port_tag_sts_ctrl
+ (port
<< 2));
541 if (dsa_is_cpu_port(ds
, port
))
544 /* add port to switch mask of CPU_PORT */
545 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
547 /* add all other ports in the same bridge to switch mask of port */
548 v
= priv
->r
->traffic_get(port
);
549 v
|= priv
->ports
[port
].pm
;
550 priv
->r
->traffic_set(port
, v
);
552 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_SABLK_CTRL
);
553 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_DABLK_CTRL
);
558 static void rtl83xx_port_disable(struct dsa_switch
*ds
, int port
)
560 struct rtl838x_switch_priv
*priv
= ds
->priv
;
563 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
564 /* you can only disable user ports */
565 if (!dsa_is_user_port(ds
, port
))
568 // BUG: This does not work on RTL931X
569 /* remove port from switch mask of CPU_PORT */
570 priv
->r
->traffic_disable(priv
->cpu_port
, port
);
572 /* remove all other ports in the same bridge from switch mask of port */
573 v
= priv
->r
->traffic_get(port
);
574 v
&= ~priv
->ports
[port
].pm
;
575 priv
->r
->traffic_set(port
, v
);
577 priv
->ports
[port
].enable
= false;
580 static int rtl83xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
581 struct ethtool_eee
*e
)
583 struct rtl838x_switch_priv
*priv
= ds
->priv
;
585 pr_debug("%s: port %d", __func__
, port
);
586 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
;
587 if (sw_r32(priv
->r
->mac_force_mode_ctrl(port
)) & BIT(9))
588 e
->advertised
|= ADVERTISED_100baseT_Full
;
590 if (sw_r32(priv
->r
->mac_force_mode_ctrl(port
)) & BIT(10))
591 e
->advertised
|= ADVERTISED_1000baseT_Full
;
593 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
594 pr_debug("enabled: %d, active %x\n", e
->eee_enabled
, e
->advertised
);
596 if (sw_r32(RTL838X_MAC_EEE_ABLTY
) & BIT(port
)) {
597 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
598 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
601 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
602 pr_debug("active: %d, lp %x\n", e
->eee_active
, e
->lp_advertised
);
607 static int rtl83xx_set_mac_eee(struct dsa_switch
*ds
, int port
,
608 struct ethtool_eee
*e
)
610 struct rtl838x_switch_priv
*priv
= ds
->priv
;
612 pr_debug("%s: port %d", __func__
, port
);
613 if (e
->eee_enabled
) {
614 pr_debug("Globally enabling EEE\n");
615 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL
);
617 if (e
->eee_enabled
) {
618 pr_debug("Enabling EEE for MAC %d\n", port
);
619 sw_w32_mask(0, 3 << 9, priv
->r
->mac_force_mode_ctrl(port
));
620 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_TX_EN
);
621 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_RX_EN
);
622 priv
->ports
[port
].eee_enabled
= true;
623 e
->eee_enabled
= true;
625 pr_debug("Disabling EEE for MAC %d\n", port
);
626 sw_w32_mask(3 << 9, 0, priv
->r
->mac_force_mode_ctrl(port
));
627 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_TX_EN
);
628 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_RX_EN
);
629 priv
->ports
[port
].eee_enabled
= false;
630 e
->eee_enabled
= false;
636 * Set Switch L2 Aging time, t is time in milliseconds
637 * t = 0: aging is disabled
639 static int rtl83xx_set_l2aging(struct dsa_switch
*ds
, u32 t
)
641 struct rtl838x_switch_priv
*priv
= ds
->priv
;
642 int t_max
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x7fffff : 0x1FFFFF;
644 /* Convert time in mseconds to internal value */
645 if (t
> 0x10000000) { /* Set to maximum */
648 if (priv
->family_id
== RTL8380_FAMILY_ID
)
649 t
= ((t
* 625) / 1000 + 127) / 128;
653 sw_w32(t
, priv
->r
->l2_ctrl_1
);
657 static int rtl83xx_port_bridge_join(struct dsa_switch
*ds
, int port
,
658 struct net_device
*bridge
)
660 struct rtl838x_switch_priv
*priv
= ds
->priv
;
661 u64 port_bitmap
= 1ULL << priv
->cpu_port
, v
;
664 pr_debug("%s %x: %d %llx", __func__
, (u32
)priv
, port
, port_bitmap
);
665 mutex_lock(&priv
->reg_mutex
);
666 for (i
= 0; i
< ds
->num_ports
; i
++) {
667 /* Add this port to the port matrix of the other ports in the
668 * same bridge. If the port is disabled, port matrix is kept
669 * and not being setup until the port becomes enabled.
671 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
672 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
674 if (priv
->ports
[i
].enable
)
675 priv
->r
->traffic_enable(i
, port
);
677 priv
->ports
[i
].pm
|= 1ULL << port
;
678 port_bitmap
|= 1ULL << i
;
682 /* Add all other ports to this port matrix. */
683 if (priv
->ports
[port
].enable
) {
684 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
685 v
= priv
->r
->traffic_get(port
);
687 priv
->r
->traffic_set(port
, v
);
689 priv
->ports
[port
].pm
|= port_bitmap
;
690 mutex_unlock(&priv
->reg_mutex
);
695 static void rtl83xx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
696 struct net_device
*bridge
)
698 struct rtl838x_switch_priv
*priv
= ds
->priv
;
699 u64 port_bitmap
= 1ULL << priv
->cpu_port
, v
;
702 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
703 mutex_lock(&priv
->reg_mutex
);
704 for (i
= 0; i
< ds
->num_ports
; i
++) {
705 /* Remove this port from the port matrix of the other ports
706 * in the same bridge. If the port is disabled, port matrix
707 * is kept and not being setup until the port becomes enabled.
708 * And the other port's port matrix cannot be broken when the
709 * other port is still a VLAN-aware port.
711 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
712 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
714 if (priv
->ports
[i
].enable
)
715 priv
->r
->traffic_disable(i
, port
);
717 priv
->ports
[i
].pm
|= 1ULL << port
;
718 port_bitmap
&= ~BIT_ULL(i
);
722 /* Add all other ports to this port matrix. */
723 if (priv
->ports
[port
].enable
) {
724 v
= priv
->r
->traffic_get(port
);
726 priv
->r
->traffic_set(port
, v
);
728 priv
->ports
[port
].pm
&= ~port_bitmap
;
730 mutex_unlock(&priv
->reg_mutex
);
733 void rtl83xx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
739 struct rtl838x_switch_priv
*priv
= ds
->priv
;
740 int n
= priv
->port_width
<< 1;
742 /* Ports above or equal CPU port can never be configured */
743 if (port
>= priv
->cpu_port
)
746 mutex_lock(&priv
->reg_mutex
);
748 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
749 * have 64 bit fields, 839x and 931x have 128 bit fields
751 if (priv
->family_id
== RTL8390_FAMILY_ID
)
753 if (priv
->family_id
== RTL9300_FAMILY_ID
)
755 if (priv
->family_id
== RTL9310_FAMILY_ID
)
758 index
= n
- (pos
>> 4) - 1;
759 bit
= (pos
<< 1) % 32;
761 priv
->r
->stp_get(priv
, msti
, port_state
);
763 pr_debug("Current state, port %d: %d\n", port
, (port_state
[index
] >> bit
) & 3);
764 port_state
[index
] &= ~(3 << bit
);
767 case BR_STATE_DISABLED
: /* 0 */
768 port_state
[index
] |= (0 << bit
);
770 case BR_STATE_BLOCKING
: /* 4 */
771 case BR_STATE_LISTENING
: /* 1 */
772 port_state
[index
] |= (1 << bit
);
774 case BR_STATE_LEARNING
: /* 2 */
775 port_state
[index
] |= (2 << bit
);
777 case BR_STATE_FORWARDING
: /* 3*/
778 port_state
[index
] |= (3 << bit
);
783 priv
->r
->stp_set(priv
, msti
, port_state
);
785 mutex_unlock(&priv
->reg_mutex
);
788 void rtl83xx_fast_age(struct dsa_switch
*ds
, int port
)
790 struct rtl838x_switch_priv
*priv
= ds
->priv
;
791 int s
= priv
->family_id
== RTL8390_FAMILY_ID
? 2 : 0;
793 pr_debug("FAST AGE port %d\n", port
);
794 mutex_lock(&priv
->reg_mutex
);
795 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
797 * 0-4: Replacing port
798 * 5-9: Flushed/replaced port
800 * 22: Entry types: 1: dynamic, 0: also static
801 * 23: Match flush port
803 * 25: Flush (0) or replace (1) L2 entries
804 * 26: Status of action (1: Start, 0: Done)
806 sw_w32(1 << (26 + s
) | 1 << (23 + s
) | port
<< (5 + (s
/ 2)), priv
->r
->l2_tbl_flush_ctrl
);
808 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(26 + s
));
810 mutex_unlock(&priv
->reg_mutex
);
813 void rtl930x_fast_age(struct dsa_switch
*ds
, int port
)
815 struct rtl838x_switch_priv
*priv
= ds
->priv
;
817 pr_debug("FAST AGE port %d\n", port
);
818 mutex_lock(&priv
->reg_mutex
);
819 sw_w32(port
<< 11, RTL930X_L2_TBL_FLUSH_CTRL
+ 4);
821 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL
);
823 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(30));
825 mutex_unlock(&priv
->reg_mutex
);
828 static int rtl83xx_vlan_filtering(struct dsa_switch
*ds
, int port
,
831 struct rtl838x_switch_priv
*priv
= ds
->priv
;
833 pr_debug("%s: port %d\n", __func__
, port
);
834 mutex_lock(&priv
->reg_mutex
);
836 if (vlan_filtering
) {
837 /* Enable ingress and egress filtering
838 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
842 * 2: Trap packet to CPU port
843 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
845 if (port
!= priv
->cpu_port
)
846 sw_w32_mask(0b10 << ((port
% 16) << 1), 0b01 << ((port
% 16) << 1),
847 priv
->r
->vlan_port_igr_filter
+ ((port
>> 5) << 2));
848 sw_w32_mask(0, BIT(port
% 32), priv
->r
->vlan_port_egr_filter
+ ((port
>> 4) << 2));
850 /* Disable ingress and egress filtering */
851 if (port
!= priv
->cpu_port
)
852 sw_w32_mask(0b11 << ((port
% 16) << 1), 0,
853 priv
->r
->vlan_port_igr_filter
+ ((port
>> 5) << 2));
854 sw_w32_mask(BIT(port
% 32), 0, priv
->r
->vlan_port_egr_filter
+ ((port
>> 4) << 2));
857 /* Do we need to do something to the CPU-Port, too? */
858 mutex_unlock(&priv
->reg_mutex
);
863 static int rtl83xx_vlan_prepare(struct dsa_switch
*ds
, int port
,
864 const struct switchdev_obj_port_vlan
*vlan
)
866 struct rtl838x_vlan_info info
;
867 struct rtl838x_switch_priv
*priv
= ds
->priv
;
869 pr_info("%s: port %d\n", __func__
, port
);
871 mutex_lock(&priv
->reg_mutex
);
873 priv
->r
->vlan_profile_dump(1);
874 priv
->r
->vlan_tables_read(1, &info
);
876 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
877 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
878 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
880 priv
->r
->vlan_set_untagged(1, info
.untagged_ports
);
881 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info
.untagged_ports
);
883 priv
->r
->vlan_set_tagged(1, &info
);
884 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info
.tagged_ports
);
886 mutex_unlock(&priv
->reg_mutex
);
890 static void rtl83xx_vlan_add(struct dsa_switch
*ds
, int port
,
891 const struct switchdev_obj_port_vlan
*vlan
)
893 struct rtl838x_vlan_info info
;
894 struct rtl838x_switch_priv
*priv
= ds
->priv
;
897 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
898 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
900 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
901 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
902 vlan
->vid_begin
, vlan
->vid_end
);
906 mutex_lock(&priv
->reg_mutex
);
908 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
) {
909 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
912 /* Set both inner and outer PVID of the port */
913 sw_w32((v
<< 16) | v
<< 2, priv
->r
->vlan_port_pb
+ (port
<< 2));
914 priv
->ports
[port
].pvid
= vlan
->vid_end
;
918 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
922 /* Get port memberships of this vlan */
923 priv
->r
->vlan_tables_read(v
, &info
);
926 if (!info
.tagged_ports
) {
928 info
.hash_mc_fid
= false;
929 info
.hash_uc_fid
= false;
933 /* sanitize untagged_ports - must be a subset */
934 if (info
.untagged_ports
& ~info
.tagged_ports
)
935 info
.untagged_ports
= 0;
937 info
.tagged_ports
|= BIT_ULL(port
);
938 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
939 info
.untagged_ports
|= BIT_ULL(port
);
941 priv
->r
->vlan_set_untagged(v
, info
.untagged_ports
);
942 pr_info("Untagged ports, VLAN %d: %llx\n", v
, info
.untagged_ports
);
944 priv
->r
->vlan_set_tagged(v
, &info
);
945 pr_info("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
948 mutex_unlock(&priv
->reg_mutex
);
951 static int rtl83xx_vlan_del(struct dsa_switch
*ds
, int port
,
952 const struct switchdev_obj_port_vlan
*vlan
)
954 struct rtl838x_vlan_info info
;
955 struct rtl838x_switch_priv
*priv
= ds
->priv
;
959 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
960 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
962 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
963 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
964 vlan
->vid_begin
, vlan
->vid_end
);
968 mutex_lock(&priv
->reg_mutex
);
969 pvid
= priv
->ports
[port
].pvid
;
971 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
972 /* Reset to default if removing the current PVID */
974 sw_w32(0, priv
->r
->vlan_port_pb
+ (port
<< 2));
976 /* Get port memberships of this vlan */
977 priv
->r
->vlan_tables_read(v
, &info
);
979 /* remove port from both tables */
980 info
.untagged_ports
&= (~BIT_ULL(port
));
981 /* always leave vid 1 */
983 info
.tagged_ports
&= (~BIT_ULL(port
));
985 priv
->r
->vlan_set_untagged(v
, info
.untagged_ports
);
986 pr_debug("Untagged ports, VLAN %d: %llx\n", v
, info
.untagged_ports
);
988 priv
->r
->vlan_set_tagged(v
, &info
);
989 pr_debug("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
991 mutex_unlock(&priv
->reg_mutex
);
996 static int rtl83xx_port_fdb_add(struct dsa_switch
*ds
, int port
,
997 const unsigned char *addr
, u16 vid
)
999 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1000 u64 mac
= ether_addr_to_u64(addr
);
1001 u32 key
= rtl83xx_hash_key(priv
, mac
, vid
);
1002 struct rtl838x_l2_entry e
;
1005 int idx
= -1, err
= 0, i
;
1007 mutex_lock(&priv
->reg_mutex
);
1008 for (i
= 0; i
< 4; i
++) {
1009 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, &e
);
1011 idx
= (key
<< 2) | i
;
1014 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1015 idx
= (key
<< 2) | i
;
1020 r
[0] = 3 << 17 | port
<< 12; // Aging and port
1023 r
[2] = (mac
& 0xffff) << 12; /* rvid = 0 */
1024 rtl83xx_write_hash(idx
, r
);
1028 /* Hash buckets full, try CAM */
1029 for (i
= 0; i
< 64; i
++) {
1030 entry
= priv
->r
->read_cam(i
, &e
);
1032 if (idx
< 0) /* First empty entry? */
1035 } else if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1036 pr_debug("Found entry in CAM\n");
1042 r
[0] = 3 << 17 | port
<< 12; // Aging
1045 r
[2] = (mac
& 0xffff) << 12; /* rvid = 0 */
1046 rtl83xx_write_cam(idx
, r
);
1051 mutex_unlock(&priv
->reg_mutex
);
1055 static int rtl83xx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1056 const unsigned char *addr
, u16 vid
)
1058 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1059 u64 mac
= ether_addr_to_u64(addr
);
1060 u32 key
= rtl83xx_hash_key(priv
, mac
, vid
);
1061 struct rtl838x_l2_entry e
;
1064 int idx
= -1, err
= 0, i
;
1066 pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__
, mac
, vid
, key
);
1067 mutex_lock(&priv
->reg_mutex
);
1068 for (i
= 0; i
< 4; i
++) {
1069 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, &e
);
1072 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1073 idx
= (key
<< 2) | i
;
1079 r
[0] = r
[1] = r
[2] = 0;
1080 rtl83xx_write_hash(idx
, r
);
1084 /* Check CAM for spillover from hash buckets */
1085 for (i
= 0; i
< 64; i
++) {
1086 entry
= priv
->r
->read_cam(i
, &e
);
1087 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1093 r
[0] = r
[1] = r
[2] = 0;
1094 rtl83xx_write_cam(idx
, r
);
1099 mutex_unlock(&priv
->reg_mutex
);
1103 static int rtl83xx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1104 dsa_fdb_dump_cb_t
*cb
, void *data
)
1106 struct rtl838x_l2_entry e
;
1107 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1113 mutex_lock(&priv
->reg_mutex
);
1115 for (i
= 0; i
< priv
->fib_entries
; i
++) {
1116 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1121 if (e
.port
== port
) {
1122 fid
= (i
& 0x3ff) | (e
.rvid
& ~0x3ff);
1123 mac
= ether_addr_to_u64(&e
.mac
[0]);
1124 pkey
= rtl838x_hash(priv
, mac
<< 12 | fid
);
1125 fid
= (pkey
& 0x3ff) | (fid
& ~0x3ff);
1126 pr_debug("-> mac %016llx, fid: %d\n", mac
, fid
);
1127 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1131 for (i
= 0; i
< 64; i
++) {
1132 priv
->r
->read_cam(i
, &e
);
1138 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1141 mutex_unlock(&priv
->reg_mutex
);
1145 static int rtl83xx_port_mirror_add(struct dsa_switch
*ds
, int port
,
1146 struct dsa_mall_mirror_tc_entry
*mirror
,
1149 /* We support 4 mirror groups, one destination port per group */
1151 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1152 int ctrl_reg
, dpm_reg
, spm_reg
;
1154 pr_debug("In %s\n", __func__
);
1156 for (group
= 0; group
< 4; group
++) {
1157 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1161 for (group
= 0; group
< 4; group
++) {
1162 if (priv
->mirror_group_ports
[group
] < 0)
1170 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1171 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1172 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1174 pr_debug("Using group %d\n", group
);
1175 mutex_lock(&priv
->reg_mutex
);
1177 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1178 /* Enable mirroring to port across VLANs (bit 11) */
1179 sw_w32(1 << 11 | (mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1181 /* Enable mirroring to destination port */
1182 sw_w32((mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1185 if (ingress
&& (priv
->r
->get_port_reg_be(spm_reg
) & (1ULL << port
))) {
1186 mutex_unlock(&priv
->reg_mutex
);
1189 if ((!ingress
) && (priv
->r
->get_port_reg_be(dpm_reg
) & (1ULL << port
))) {
1190 mutex_unlock(&priv
->reg_mutex
);
1195 priv
->r
->mask_port_reg_be(0, 1ULL << port
, spm_reg
);
1197 priv
->r
->mask_port_reg_be(0, 1ULL << port
, dpm_reg
);
1199 priv
->mirror_group_ports
[group
] = mirror
->to_local_port
;
1200 mutex_unlock(&priv
->reg_mutex
);
1204 static void rtl83xx_port_mirror_del(struct dsa_switch
*ds
, int port
,
1205 struct dsa_mall_mirror_tc_entry
*mirror
)
1208 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1209 int ctrl_reg
, dpm_reg
, spm_reg
;
1211 pr_debug("In %s\n", __func__
);
1212 for (group
= 0; group
< 4; group
++) {
1213 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1219 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1220 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1221 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1223 mutex_lock(&priv
->reg_mutex
);
1224 if (mirror
->ingress
) {
1225 /* Ingress, clear source port matrix */
1226 priv
->r
->mask_port_reg_be(1ULL << port
, 0, spm_reg
);
1228 /* Egress, clear destination port matrix */
1229 priv
->r
->mask_port_reg_be(1ULL << port
, 0, dpm_reg
);
1232 if (!(sw_r32(spm_reg
) || sw_r32(dpm_reg
))) {
1233 priv
->mirror_group_ports
[group
] = -1;
1234 sw_w32(0, ctrl_reg
);
1237 mutex_unlock(&priv
->reg_mutex
);
1240 int dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
)
1244 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1246 if (phy_addr
>= 24 && phy_addr
<= 27
1247 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
1250 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
1254 read_phy(phy_addr
, 0, phy_reg
, &val
);
1258 int dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
)
1261 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1263 if (phy_addr
>= 24 && phy_addr
<= 27
1264 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
1267 sw_w32(val
, RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2));
1270 return write_phy(phy_addr
, 0, phy_reg
, val
);
1273 const struct dsa_switch_ops rtl83xx_switch_ops
= {
1274 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
1275 .setup
= rtl83xx_setup
,
1277 .phy_read
= dsa_phy_read
,
1278 .phy_write
= dsa_phy_write
,
1280 .phylink_validate
= rtl83xx_phylink_validate
,
1281 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
1282 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
1283 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
1284 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
1286 .get_strings
= rtl83xx_get_strings
,
1287 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
1288 .get_sset_count
= rtl83xx_get_sset_count
,
1290 .port_enable
= rtl83xx_port_enable
,
1291 .port_disable
= rtl83xx_port_disable
,
1293 .get_mac_eee
= rtl83xx_get_mac_eee
,
1294 .set_mac_eee
= rtl83xx_set_mac_eee
,
1296 .set_ageing_time
= rtl83xx_set_l2aging
,
1297 .port_bridge_join
= rtl83xx_port_bridge_join
,
1298 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
1299 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
1300 .port_fast_age
= rtl83xx_fast_age
,
1302 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
1303 .port_vlan_prepare
= rtl83xx_vlan_prepare
,
1304 .port_vlan_add
= rtl83xx_vlan_add
,
1305 .port_vlan_del
= rtl83xx_vlan_del
,
1307 .port_fdb_add
= rtl83xx_port_fdb_add
,
1308 .port_fdb_del
= rtl83xx_port_fdb_del
,
1309 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
1311 .port_mirror_add
= rtl83xx_port_mirror_add
,
1312 .port_mirror_del
= rtl83xx_port_mirror_del
,
1315 const struct dsa_switch_ops rtl930x_switch_ops
= {
1316 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
1317 .setup
= rtl930x_setup
,
1319 .phy_read
= dsa_phy_read
,
1320 .phy_write
= dsa_phy_write
,
1322 .phylink_validate
= rtl83xx_phylink_validate
,
1323 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
1324 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
1325 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
1326 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
1328 .get_strings
= rtl83xx_get_strings
,
1329 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
1330 .get_sset_count
= rtl83xx_get_sset_count
,
1332 .port_enable
= rtl83xx_port_enable
,
1333 .port_disable
= rtl83xx_port_disable
,
1335 .set_ageing_time
= rtl83xx_set_l2aging
,
1336 .port_bridge_join
= rtl83xx_port_bridge_join
,
1337 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
1338 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
1339 .port_fast_age
= rtl930x_fast_age
,
1341 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
1342 .port_vlan_prepare
= rtl83xx_vlan_prepare
,
1343 .port_vlan_add
= rtl83xx_vlan_add
,
1344 .port_vlan_del
= rtl83xx_vlan_del
,
1346 .port_fdb_add
= rtl83xx_port_fdb_add
,
1347 .port_fdb_del
= rtl83xx_port_fdb_del
,
1348 .port_fdb_dump
= rtl83xx_port_fdb_dump
,