1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
4 * Copyright (C) 2020 B. Koblitz
7 #include <linux/module.h>
8 #include <linux/delay.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
14 #include <asm/mach-rtl838x/mach-rtl83xx.h>
15 #include "rtl83xx-phy.h"
18 extern struct rtl83xx_soc_info soc_info
;
19 extern struct mutex smi_lock
;
21 static const struct firmware rtl838x_8380_fw
;
22 static const struct firmware rtl838x_8214fc_fw
;
23 static const struct firmware rtl838x_8218b_fw
;
26 static int read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
28 if (soc_info
.family
== RTL8390_FAMILY_ID
)
29 return rtl839x_read_phy(port
, page
, reg
, val
);
31 return rtl838x_read_phy(port
, page
, reg
, val
);
34 static int write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
36 if (soc_info
.family
== RTL8390_FAMILY_ID
)
37 return rtl839x_write_phy(port
, page
, reg
, val
);
39 return rtl838x_write_phy(port
, page
, reg
, val
);
42 static void int_phy_on_off(int mac
, bool on
)
46 read_phy(mac
, 0, 0, &val
);
48 write_phy(mac
, 0, 0, val
& ~(1 << 11));
50 write_phy(mac
, 0, 0, val
| (1 << 11));
53 static void rtl8214fc_on_off(int mac
, bool on
)
58 write_phy(mac
, 4095, 30, 3);
59 read_phy(mac
, 0, 16, &val
);
61 write_phy(mac
, 0, 16, val
& ~(1 << 11));
63 write_phy(mac
, 0, 16, val
| (1 << 11));
66 write_phy(mac
, 4095, 30, 1);
67 read_phy(mac
, 0, 16, &val
);
69 write_phy(mac
, 0xa40, 16, val
& ~(1 << 11));
71 write_phy(mac
, 0xa40, 16, val
| (1 << 11));
74 static void phy_reset(int mac
)
78 read_phy(mac
, 0, 0, &val
);
79 write_phy(mac
, 0, 0, val
| (0x1 << 15));
82 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
83 * ports of the RTL838x SoCs
85 static int rtl8380_read_status(struct phy_device
*phydev
)
89 err
= genphy_read_status(phydev
);
92 phydev
->speed
= SPEED_1000
;
93 phydev
->duplex
= DUPLEX_FULL
;
99 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
100 * ports of the RTL8393 SoC
102 static int rtl8393_read_status(struct phy_device
*phydev
)
106 int phy_addr
= phydev
->mdio
.addr
;
109 err
= genphy_read_status(phydev
);
114 phydev
->speed
= SPEED_100
;
115 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
118 v
= sw_r32(RTL839X_SDS12_13_XSG0
+ offset
+ 0x80);
119 if (!(v
& (1 << 13)) && (v
& (1 << 6)))
120 phydev
->speed
= SPEED_1000
;
121 phydev
->duplex
= DUPLEX_FULL
;
127 static struct fw_header
*rtl838x_request_fw(struct phy_device
*phydev
,
128 const struct firmware
*fw
,
131 struct device
*dev
= &phydev
->mdio
.dev
;
134 uint32_t checksum
, my_checksum
;
136 err
= request_firmware(&fw
, name
, dev
);
140 if (fw
->size
< sizeof(struct fw_header
)) {
141 pr_err("Firmware size too small.\n");
146 h
= (struct fw_header
*) fw
->data
;
147 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw
->size
, h
->magic
);
149 if (h
->magic
!= 0x83808380) {
150 pr_err("Wrong firmware file: MAGIC mismatch.\n");
154 checksum
= h
->checksum
;
156 my_checksum
= ~crc32(0xFFFFFFFFU
, fw
->data
, fw
->size
);
157 if (checksum
!= my_checksum
) {
158 pr_err("Firmware checksum mismatch.\n");
162 h
->checksum
= checksum
;
166 dev_err(dev
, "Unable to load firmware %s (%d)\n", name
, err
);
170 static int rtl8390_configure_generic(struct phy_device
*phydev
)
173 int mac
= phydev
->mdio
.addr
;
175 read_phy(mac
, 0, 2, &val
);
177 read_phy(mac
, 0, 3, &val
);
179 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
181 /* Read internal PHY ID */
182 write_phy(mac
, 31, 27, 0x0002);
183 read_phy(mac
, 31, 28, &val
);
185 /* Internal RTL8218B, version 2 */
186 phydev_info(phydev
, "Detected unknown %x\n", val
);
190 static int rtl8380_configure_int_rtl8218b(struct phy_device
*phydev
)
194 int mac
= phydev
->mdio
.addr
;
196 u32
*rtl838x_6275B_intPhy_perport
;
197 u32
*rtl8218b_6276B_hwEsd_perport
;
200 read_phy(mac
, 0, 2, &val
);
202 read_phy(mac
, 0, 3, &val
);
204 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
206 /* Read internal PHY ID */
207 write_phy(mac
, 31, 27, 0x0002);
208 read_phy(mac
, 31, 28, &val
);
210 phydev_err(phydev
, "Expected internal RTL8218B, found PHY-ID %x\n", val
);
214 /* Internal RTL8218B, version 2 */
215 phydev_info(phydev
, "Detected internal RTL8218B\n");
217 h
= rtl838x_request_fw(phydev
, &rtl838x_8380_fw
, FIRMWARE_838X_8380_1
);
221 if (h
->phy
!= 0x83800000) {
222 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
226 rtl838x_6275B_intPhy_perport
= (void *)h
+ sizeof(struct fw_header
)
229 rtl8218b_6276B_hwEsd_perport
= (void *)h
+ sizeof(struct fw_header
)
232 if (sw_r32(RTL838X_DMY_REG31
) == 0x1)
235 read_phy(mac
, 0, 0, &val
);
237 int_phy_on_off(mac
, true);
242 /* Ready PHY for patch */
243 for (p
= 0; p
< 8; p
++) {
244 write_phy(mac
+ p
, 0xfff, 0x1f, 0x0b82);
245 write_phy(mac
+ p
, 0xfff, 0x10, 0x0010);
248 for (p
= 0; p
< 8; p
++) {
249 for (i
= 0; i
< 100 ; i
++) {
250 read_phy(mac
+ p
, 0x0b80, 0x10, &val
);
256 "ERROR: Port %d not ready for patch.\n",
261 for (p
= 0; p
< 8; p
++) {
263 while (rtl838x_6275B_intPhy_perport
[i
* 2]) {
264 write_phy(mac
+ p
, 0xfff,
265 rtl838x_6275B_intPhy_perport
[i
* 2],
266 rtl838x_6275B_intPhy_perport
[i
* 2 + 1]);
270 while (rtl8218b_6276B_hwEsd_perport
[i
* 2]) {
271 write_phy(mac
+ p
, 0xfff,
272 rtl8218b_6276B_hwEsd_perport
[i
* 2],
273 rtl8218b_6276B_hwEsd_perport
[i
* 2 + 1]);
280 static int rtl8380_configure_ext_rtl8218b(struct phy_device
*phydev
)
282 u32 val
, ipd
, phy_id
;
284 int mac
= phydev
->mdio
.addr
;
286 u32
*rtl8380_rtl8218b_perchip
;
287 u32
*rtl8218B_6276B_rtl8380_perport
;
288 u32
*rtl8380_rtl8218b_perport
;
290 if (soc_info
.family
== RTL8380_FAMILY_ID
&& mac
!= 0 && mac
!= 16) {
291 phydev_err(phydev
, "External RTL8218B must have PHY-IDs 0 or 16!\n");
294 read_phy(mac
, 0, 2, &val
);
296 read_phy(mac
, 0, 3, &val
);
298 pr_info("Phy on MAC %d: %x\n", mac
, phy_id
);
300 /* Read internal PHY ID */
301 write_phy(mac
, 31, 27, 0x0002);
302 read_phy(mac
, 31, 28, &val
);
304 phydev_err(phydev
, "Expected external RTL8218B, found PHY-ID %x\n", val
);
307 phydev_info(phydev
, "Detected external RTL8218B\n");
309 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8218b_1
);
313 if (h
->phy
!= 0x8218b000) {
314 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
318 rtl8380_rtl8218b_perchip
= (void *)h
+ sizeof(struct fw_header
)
321 rtl8218B_6276B_rtl8380_perport
= (void *)h
+ sizeof(struct fw_header
)
324 rtl8380_rtl8218b_perport
= (void *)h
+ sizeof(struct fw_header
)
327 read_phy(mac
, 0, 0, &val
);
329 int_phy_on_off(mac
, true);
334 /* Get Chip revision */
335 write_phy(mac
, 0xfff, 0x1f, 0x0);
336 write_phy(mac
, 0xfff, 0x1b, 0x4);
337 read_phy(mac
, 0xfff, 0x1c, &val
);
340 while (rtl8380_rtl8218b_perchip
[i
* 3]
341 && rtl8380_rtl8218b_perchip
[i
* 3 + 1]) {
342 write_phy(mac
+ rtl8380_rtl8218b_perchip
[i
* 3],
343 0xfff, rtl8380_rtl8218b_perchip
[i
* 3 + 1],
344 rtl8380_rtl8218b_perchip
[i
* 3 + 2]);
349 for (i
= 0; i
< 8; i
++) {
350 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
351 write_phy(mac
+ i
, 0xfff, 0x00, 0x1140);
356 for (i
= 0; i
< 8; i
++) {
357 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0b82);
358 write_phy(mac
+ i
, 0xfff, 0x10, 0x0010);
362 /* Verify patch readiness */
363 for (i
= 0; i
< 8; i
++) {
364 for (l
= 0; l
< 100; l
++) {
365 read_phy(mac
+ i
, 0xb80, 0x10, &val
);
370 phydev_err(phydev
, "Could not patch PHY\n");
375 /* Use Broadcast ID method for patching */
376 write_phy(mac
, 0xfff, 0x1f, 0x0000);
377 write_phy(mac
, 0xfff, 0x1d, 0x0008);
378 write_phy(mac
, 0xfff, 0x1f, 0x0266);
379 write_phy(mac
, 0xfff, 0x16, 0xff00 + mac
);
380 write_phy(mac
, 0xfff, 0x1f, 0x0000);
381 write_phy(mac
, 0xfff, 0x1d, 0x0000);
384 write_phy(mac
, 0xfff, 30, 8);
385 write_phy(mac
, 0x26e, 17, 0xb);
386 write_phy(mac
, 0x26e, 16, 0x2);
388 read_phy(mac
, 0x26e, 19, &ipd
);
389 write_phy(mac
, 0, 30, 0);
390 ipd
= (ipd
>> 4) & 0xf;
393 while (rtl8218B_6276B_rtl8380_perport
[i
* 2]) {
394 write_phy(mac
, 0xfff, rtl8218B_6276B_rtl8380_perport
[i
* 2],
395 rtl8218B_6276B_rtl8380_perport
[i
* 2 + 1]);
399 /*Disable broadcast ID*/
400 write_phy(mac
, 0xfff, 0x1f, 0x0000);
401 write_phy(mac
, 0xfff, 0x1d, 0x0008);
402 write_phy(mac
, 0xfff, 0x1f, 0x0266);
403 write_phy(mac
, 0xfff, 0x16, 0x00 + mac
);
404 write_phy(mac
, 0xfff, 0x1f, 0x0000);
405 write_phy(mac
, 0xfff, 0x1d, 0x0000);
411 static int rtl8218b_ext_match_phy_device(struct phy_device
*phydev
)
413 int addr
= phydev
->mdio
.addr
;
415 /* Both the RTL8214FC and the external RTL8218B have the same
416 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
417 * at PHY IDs 0-7, while the RTL8214FC must be attached via
418 * the pair of SGMII/1000Base-X with higher PHY-IDs
420 if (soc_info
.family
== RTL8380_FAMILY_ID
)
421 return phydev
->phy_id
== PHY_ID_RTL8218B_E
&& addr
< 8;
423 return phydev
->phy_id
== PHY_ID_RTL8218B_E
;
427 * Read an mmd register of the PHY
429 static int rtl83xx_read_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32
*val
)
433 mutex_lock(&smi_lock
);
435 if (rtl838x_smi_wait_op(10000))
438 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
441 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
443 v
= addr
<< 16 | reg
;
444 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
446 /* mmd-access | read | cmd-start */
447 v
= 1 << 1 | 0 << 2 | 1;
448 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
450 if (rtl838x_smi_wait_op(10000))
453 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
455 mutex_unlock(&smi_lock
);
459 mutex_unlock(&smi_lock
);
464 * Write to an mmd register of the PHY
466 static int rtl838x_write_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32 val
)
470 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port
, addr
, reg
, val
);
472 mutex_lock(&smi_lock
);
474 if (rtl838x_smi_wait_op(10000))
477 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
480 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
482 sw_w32_mask(0x1f << 16, addr
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
483 sw_w32_mask(0xffff, reg
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
484 /* mmd-access | write | cmd-start */
485 v
= 1 << 1 | 1 << 2 | 1;
486 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
488 if (rtl838x_smi_wait_op(10000))
491 mutex_unlock(&smi_lock
);
495 mutex_unlock(&smi_lock
);
499 static int rtl8218b_read_mmd(struct phy_device
*phydev
,
500 int devnum
, u16 regnum
)
504 int addr
= phydev
->mdio
.addr
;
506 ret
= rtl83xx_read_mmd_phy(addr
, devnum
, regnum
, &val
);
512 static int rtl8218b_write_mmd(struct phy_device
*phydev
,
513 int devnum
, u16 regnum
, u16 val
)
515 int addr
= phydev
->mdio
.addr
;
517 return rtl838x_write_mmd_phy(addr
, devnum
, regnum
, val
);
520 static void rtl8380_rtl8214fc_media_set(int mac
, bool set_fibre
)
522 int base
= mac
- (mac
% 4);
523 static int reg
[] = {16, 19, 20, 21};
524 int val
, media
, power
;
526 pr_info("%s: port %d, set_fibre: %d\n", __func__
, mac
, set_fibre
);
527 write_phy(base
, 0xfff, 29, 8);
528 read_phy(base
, 0x266, reg
[mac
% 4], &val
);
530 media
= (val
>> 10) & 0x3;
531 pr_info("Current media %x\n", media
);
533 pr_info("Powering off COPPER\n");
534 write_phy(base
, 0xfff, 29, 1);
535 /* Ensure power is off */
536 read_phy(base
, 0xa40, 16, &power
);
537 if (!(power
& (1 << 11)))
538 write_phy(base
, 0xa40, 16, power
| (1 << 11));
540 pr_info("Powering off FIBRE");
541 write_phy(base
, 0xfff, 29, 3);
542 /* Ensure power is off */
543 read_phy(base
, 0xa40, 16, &power
);
544 if (!(power
& (1 << 11)))
545 write_phy(base
, 0xa40, 16, power
| (1 << 11));
555 write_phy(base
, 0xfff, 29, 8);
556 write_phy(base
, 0x266, reg
[mac
% 4], val
);
557 write_phy(base
, 0xfff, 29, 0);
560 pr_info("Powering on FIBRE");
561 write_phy(base
, 0xfff, 29, 3);
562 /* Ensure power is off */
563 read_phy(base
, 0xa40, 16, &power
);
564 if (power
& (1 << 11))
565 write_phy(base
, 0xa40, 16, power
& ~(1 << 11));
567 pr_info("Powering on COPPER\n");
568 write_phy(base
, 0xfff, 29, 1);
569 /* Ensure power is off */
570 read_phy(base
, 0xa40, 16, &power
);
571 if (power
& (1 << 11))
572 write_phy(base
, 0xa40, 16, power
& ~(1 << 11));
575 write_phy(base
, 0xfff, 29, 0);
578 static bool rtl8380_rtl8214fc_media_is_fibre(int mac
)
580 int base
= mac
- (mac
% 4);
581 static int reg
[] = {16, 19, 20, 21};
584 write_phy(base
, 0xfff, 29, 8);
585 read_phy(base
, 0x266, reg
[mac
% 4], &val
);
586 write_phy(base
, 0xfff, 29, 0);
592 static int rtl8214fc_set_port(struct phy_device
*phydev
, int port
)
594 bool is_fibre
= (port
== PORT_FIBRE
? true : false);
595 int addr
= phydev
->mdio
.addr
;
597 pr_debug("%s port %d to %d\n", __func__
, addr
, port
);
599 rtl8380_rtl8214fc_media_set(addr
, is_fibre
);
603 static int rtl8214fc_get_port(struct phy_device
*phydev
)
605 int addr
= phydev
->mdio
.addr
;
607 pr_debug("%s: port %d\n", __func__
, addr
);
608 if (rtl8380_rtl8214fc_media_is_fibre(addr
))
613 static void rtl8218b_eee_set_u_boot(int port
, bool enable
)
618 /* Set GPHY page to copper */
619 write_phy(port
, 0, 30, 0x0001);
620 read_phy(port
, 0, 0, &val
);
621 an_enabled
= val
& (1 << 12);
624 /* 100/1000M EEE Capability */
625 write_phy(port
, 0, 13, 0x0007);
626 write_phy(port
, 0, 14, 0x003C);
627 write_phy(port
, 0, 13, 0x4007);
628 write_phy(port
, 0, 14, 0x0006);
630 read_phy(port
, 0x0A43, 25, &val
);
632 write_phy(port
, 0x0A43, 25, val
);
634 /* 100/1000M EEE Capability */
635 write_phy(port
, 0, 13, 0x0007);
636 write_phy(port
, 0, 14, 0x003C);
637 write_phy(port
, 0, 13, 0x0007);
638 write_phy(port
, 0, 14, 0x0000);
640 read_phy(port
, 0x0A43, 25, &val
);
642 write_phy(port
, 0x0A43, 25, val
);
645 /* Restart AN if enabled */
647 read_phy(port
, 0, 0, &val
);
648 val
|= (1 << 12) | (1 << 9);
649 write_phy(port
, 0, 0, val
);
652 /* GPHY page back to auto*/
653 write_phy(port
, 0xa42, 29, 0);
657 static void rtl8380_rtl8218b_eee_set(int port
, bool enable
)
662 pr_debug("In %s %d, enable %d\n", __func__
, port
, enable
);
663 /* Set GPHY page to copper */
664 write_phy(port
, 0xa42, 29, 0x0001);
666 read_phy(port
, 0, 0, &val
);
667 an_enabled
= val
& (1 << 12);
670 read_phy(port
, 0xa43, 25, &val
);
672 write_phy(port
, 0xa43, 25, val
);
674 /* 100M / 1000M EEE */
676 rtl838x_write_mmd_phy(port
, 7, 60, 0x6);
678 rtl838x_write_mmd_phy(port
, 7, 60, 0);
680 /* 500M EEE ability */
681 read_phy(port
, 0xa42, 20, &val
);
686 write_phy(port
, 0xa42, 20, val
);
688 /* Restart AN if enabled */
690 read_phy(port
, 0, 0, &val
);
691 val
|= (1 << 12) | (1 << 9);
692 write_phy(port
, 0, 0, val
);
695 /* GPHY page back to auto*/
696 write_phy(port
, 0xa42, 29, 0);
699 static int rtl8218b_get_eee(struct phy_device
*phydev
,
700 struct ethtool_eee
*e
)
703 int addr
= phydev
->mdio
.addr
;
705 pr_debug("In %s, port %d\n", __func__
, addr
);
707 /* Set GPHY page to copper */
708 write_phy(addr
, 0xa42, 29, 0x0001);
710 rtl83xx_read_mmd_phy(addr
, 7, 60, &val
);
711 if (e
->eee_enabled
&& (!!(val
& (1 << 7))))
712 e
->eee_enabled
= !!(val
& (1 << 7));
716 /* GPHY page to auto */
717 write_phy(addr
, 0xa42, 29, 0x0000);
723 static void rtl8380_rtl8218b_green_set(int mac
, bool enable
)
727 /* Set GPHY page to copper */
728 write_phy(mac
, 0xa42, 29, 0x0001);
730 write_phy(mac
, 0, 27, 0x8011);
731 read_phy(mac
, 0, 28, &val
);
734 write_phy(mac
, 0, 27, 0x8011);
735 write_phy(mac
, 0, 28, val
);
738 write_phy(mac
, 0, 27, 0x8011);
739 write_phy(mac
, 0, 28, val
);
742 /* GPHY page to auto */
743 write_phy(mac
, 0xa42, 29, 0x0000);
747 static int rtl8380_rtl8214fc_get_green(struct phy_device
*phydev
, struct ethtool_eee
*e
)
750 int addr
= phydev
->mdio
.addr
;
752 pr_debug("In %s %d\n", __func__
, addr
);
753 /* Set GPHY page to copper */
754 write_phy(addr
, 0xa42, 29, 0x0001);
756 write_phy(addr
, 0, 27, 0x8011);
757 read_phy(addr
, 0, 28, &val
);
758 if (e
->eee_enabled
&& (!!(val
& (1 << 9))))
759 e
->eee_enabled
= !!(val
& (1 << 9));
763 /* GPHY page to auto */
764 write_phy(addr
, 0xa42, 29, 0x0000);
769 static int rtl8214fc_set_eee(struct phy_device
*phydev
,
770 struct ethtool_eee
*e
)
773 int addr
= phydev
->mdio
.addr
;
775 pr_debug("In %s port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
777 if (rtl8380_rtl8214fc_media_is_fibre(addr
)) {
778 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", addr
);
782 pollMask
= sw_r32(RTL838X_SMI_POLL_CTRL
);
783 sw_w32(0, RTL838X_SMI_POLL_CTRL
);
784 rtl8218b_eee_set_u_boot(addr
, (bool) e
->eee_enabled
);
785 sw_w32(pollMask
, RTL838X_SMI_POLL_CTRL
);
789 static int rtl8214fc_get_eee(struct phy_device
*phydev
,
790 struct ethtool_eee
*e
)
792 int addr
= phydev
->mdio
.addr
;
794 pr_debug("In %s port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
795 if (rtl8380_rtl8214fc_media_is_fibre(addr
)) {
796 netdev_err(phydev
->attached_dev
, "Port %d configured for FIBRE", addr
);
800 return rtl8218b_get_eee(phydev
, e
);
803 static int rtl8218b_set_eee(struct phy_device
*phydev
,
804 struct ethtool_eee
*e
)
807 int addr
= phydev
->mdio
.addr
;
809 pr_debug("In %s, port %d, enabled %d\n", __func__
, addr
, e
->eee_enabled
);
811 pollMask
= sw_r32(RTL838X_SMI_POLL_CTRL
);
812 sw_w32(0, RTL838X_SMI_POLL_CTRL
);
813 rtl8218b_eee_set_u_boot(addr
, (bool) e
->eee_enabled
);
814 sw_w32(pollMask
, RTL838X_SMI_POLL_CTRL
);
819 static int rtl8214c_match_phy_device(struct phy_device
*phydev
)
821 return phydev
->phy_id
== PHY_ID_RTL8214C
;
824 static int rtl8380_configure_rtl8214c(struct phy_device
*phydev
)
827 int mac
= phydev
->mdio
.addr
;
829 read_phy(mac
, 0, 2, &val
);
831 read_phy(mac
, 0, 3, &val
);
833 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
835 phydev_info(phydev
, "Detected external RTL8214C\n");
838 write_phy(mac
, 0xa42, 29, 0);
842 static int rtl8380_configure_rtl8214fc(struct phy_device
*phydev
)
844 u32 phy_id
, val
, page
= 0;
846 int mac
= phydev
->mdio
.addr
;
848 u32
*rtl8380_rtl8214fc_perchip
;
849 u32
*rtl8380_rtl8214fc_perport
;
851 read_phy(mac
, 0, 2, &val
);
853 read_phy(mac
, 0, 3, &val
);
855 pr_debug("Phy on MAC %d: %x\n", mac
, phy_id
);
857 /* Read internal PHY id */
858 write_phy(mac
, 0, 30, 0x0001);
859 write_phy(mac
, 0, 31, 0x0a42);
860 write_phy(mac
, 31, 27, 0x0002);
861 read_phy(mac
, 31, 28, &val
);
863 phydev_err(phydev
, "Expected external RTL8214FC, found PHY-ID %x\n", val
);
866 phydev_info(phydev
, "Detected external RTL8214FC\n");
868 h
= rtl838x_request_fw(phydev
, &rtl838x_8214fc_fw
, FIRMWARE_838X_8214FC_1
);
872 if (h
->phy
!= 0x8214fc00) {
873 phydev_err(phydev
, "Wrong firmware file: PHY mismatch.\n");
877 rtl8380_rtl8214fc_perchip
= (void *)h
+ sizeof(struct fw_header
)
880 rtl8380_rtl8214fc_perport
= (void *)h
+ sizeof(struct fw_header
)
883 /* detect phy version */
884 write_phy(mac
, 0xfff, 27, 0x0004);
885 read_phy(mac
, 0xfff, 28, &val
);
887 read_phy(mac
, 0, 16, &val
);
889 rtl8214fc_on_off(mac
, true);
894 write_phy(mac
, 0, 30, 0x0001);
897 while (rtl8380_rtl8214fc_perchip
[i
* 3]
898 && rtl8380_rtl8214fc_perchip
[i
* 3 + 1]) {
899 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x1f)
900 page
= rtl8380_rtl8214fc_perchip
[i
* 3 + 2];
901 if (rtl8380_rtl8214fc_perchip
[i
* 3 + 1] == 0x13 && page
== 0x260) {
902 read_phy(mac
+ rtl8380_rtl8214fc_perchip
[i
* 3], 0x260, 13, &val
);
903 val
= (val
& 0x1f00) | (rtl8380_rtl8214fc_perchip
[i
* 3 + 2]
905 write_phy(mac
+ rtl8380_rtl8214fc_perchip
[i
* 3],
906 0xfff, rtl8380_rtl8214fc_perchip
[i
* 3 + 1], val
);
908 write_phy(mac
+ rtl8380_rtl8214fc_perchip
[i
* 3],
909 0xfff, rtl8380_rtl8214fc_perchip
[i
* 3 + 1],
910 rtl8380_rtl8214fc_perchip
[i
* 3 + 2]);
915 /* Force copper medium */
916 for (i
= 0; i
< 4; i
++) {
917 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
918 write_phy(mac
+ i
, 0xfff, 0x1e, 0x0001);
922 for (i
= 0; i
< 4; i
++) {
923 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
924 write_phy(mac
+ i
, 0xfff, 0x00, 0x1140);
928 /* Disable Autosensing */
929 for (i
= 0; i
< 4; i
++) {
930 for (l
= 0; l
< 100; l
++) {
931 read_phy(mac
+ i
, 0x0a42, 0x10, &val
);
932 if ((val
& 0x7) >= 3)
936 phydev_err(phydev
, "Could not disable autosensing\n");
942 for (i
= 0; i
< 4; i
++) {
943 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0b82);
944 write_phy(mac
+ i
, 0xfff, 0x10, 0x0010);
948 /* Verify patch readiness */
949 for (i
= 0; i
< 4; i
++) {
950 for (l
= 0; l
< 100; l
++) {
951 read_phy(mac
+ i
, 0xb80, 0x10, &val
);
956 phydev_err(phydev
, "Could not patch PHY\n");
961 /* Use Broadcast ID method for patching */
962 write_phy(mac
, 0xfff, 0x1f, 0x0000);
963 write_phy(mac
, 0xfff, 0x1d, 0x0008);
964 write_phy(mac
, 0xfff, 0x1f, 0x0266);
965 write_phy(mac
, 0xfff, 0x16, 0xff00 + mac
);
966 write_phy(mac
, 0xfff, 0x1f, 0x0000);
967 write_phy(mac
, 0xfff, 0x1d, 0x0000);
971 while (rtl8380_rtl8214fc_perport
[i
* 2]) {
972 write_phy(mac
, 0xfff, rtl8380_rtl8214fc_perport
[i
* 2],
973 rtl8380_rtl8214fc_perport
[i
* 2 + 1]);
977 /*Disable broadcast ID*/
978 write_phy(mac
, 0xfff, 0x1f, 0x0000);
979 write_phy(mac
, 0xfff, 0x1d, 0x0008);
980 write_phy(mac
, 0xfff, 0x1f, 0x0266);
981 write_phy(mac
, 0xfff, 0x16, 0x00 + mac
);
982 write_phy(mac
, 0xfff, 0x1f, 0x0000);
983 write_phy(mac
, 0xfff, 0x1d, 0x0000);
986 /* Auto medium selection */
987 for (i
= 0; i
< 4; i
++) {
988 write_phy(mac
+ i
, 0xfff, 0x1f, 0x0000);
989 write_phy(mac
+ i
, 0xfff, 0x1e, 0x0000);
995 static int rtl8214fc_match_phy_device(struct phy_device
*phydev
)
997 int addr
= phydev
->mdio
.addr
;
999 return phydev
->phy_id
== PHY_ID_RTL8214FC
&& addr
>= 24;
1002 static int rtl8380_configure_serdes(struct phy_device
*phydev
)
1007 struct fw_header
*h
;
1008 u32
*rtl8380_sds_take_reset
;
1009 u32
*rtl8380_sds_common
;
1010 u32
*rtl8380_sds01_qsgmii_6275b
;
1011 u32
*rtl8380_sds23_qsgmii_6275b
;
1012 u32
*rtl8380_sds4_fiber_6275b
;
1013 u32
*rtl8380_sds5_fiber_6275b
;
1014 u32
*rtl8380_sds_reset
;
1015 u32
*rtl8380_sds_release_reset
;
1017 phydev_info(phydev
, "Detected internal RTL8380 SERDES\n");
1019 h
= rtl838x_request_fw(phydev
, &rtl838x_8218b_fw
, FIRMWARE_838X_8380_1
);
1023 if (h
->magic
!= 0x83808380) {
1024 phydev_err(phydev
, "Wrong firmware file: magic number mismatch.\n");
1028 rtl8380_sds_take_reset
= (void *)h
+ sizeof(struct fw_header
)
1029 + h
->parts
[0].start
;
1031 rtl8380_sds_common
= (void *)h
+ sizeof(struct fw_header
)
1032 + h
->parts
[1].start
;
1034 rtl8380_sds01_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
)
1035 + h
->parts
[2].start
;
1037 rtl8380_sds23_qsgmii_6275b
= (void *)h
+ sizeof(struct fw_header
)
1038 + h
->parts
[3].start
;
1040 rtl8380_sds4_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
)
1041 + h
->parts
[4].start
;
1043 rtl8380_sds5_fiber_6275b
= (void *)h
+ sizeof(struct fw_header
)
1044 + h
->parts
[5].start
;
1046 rtl8380_sds_reset
= (void *)h
+ sizeof(struct fw_header
)
1047 + h
->parts
[6].start
;
1049 rtl8380_sds_release_reset
= (void *)h
+ sizeof(struct fw_header
)
1050 + h
->parts
[7].start
;
1052 /* Back up serdes power off value */
1053 sds_conf_value
= sw_r32(RTL838X_SDS_CFG_REG
);
1054 pr_info("SDS power down value: %x\n", sds_conf_value
);
1056 /* take serdes into reset */
1058 while (rtl8380_sds_take_reset
[2 * i
]) {
1059 sw_w32(rtl8380_sds_take_reset
[2 * i
+ 1], rtl8380_sds_take_reset
[2 * i
]);
1064 /* apply common serdes patch */
1066 while (rtl8380_sds_common
[2 * i
]) {
1067 sw_w32(rtl8380_sds_common
[2 * i
+ 1], rtl8380_sds_common
[2 * i
]);
1072 /* internal R/W enable */
1073 sw_w32(3, RTL838X_INT_RW_CTRL
);
1075 /* SerDes ports 4 and 5 are FIBRE ports */
1076 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL
);
1078 /* SerDes module settings, SerDes 0-3 are QSGMII */
1079 v
= 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1080 /* SerDes 4 and 5 are 1000BX FIBRE */
1081 v
|= 0x4 << 5 | 0x4;
1082 sw_w32(v
, RTL838X_SDS_MODE_SEL
);
1084 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL
));
1085 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL
);
1087 while (rtl8380_sds01_qsgmii_6275b
[2 * i
]) {
1088 sw_w32(rtl8380_sds01_qsgmii_6275b
[2 * i
+ 1],
1089 rtl8380_sds01_qsgmii_6275b
[2 * i
]);
1094 while (rtl8380_sds23_qsgmii_6275b
[2 * i
]) {
1095 sw_w32(rtl8380_sds23_qsgmii_6275b
[2 * i
+ 1], rtl8380_sds23_qsgmii_6275b
[2 * i
]);
1100 while (rtl8380_sds4_fiber_6275b
[2 * i
]) {
1101 sw_w32(rtl8380_sds4_fiber_6275b
[2 * i
+ 1], rtl8380_sds4_fiber_6275b
[2 * i
]);
1106 while (rtl8380_sds5_fiber_6275b
[2 * i
]) {
1107 sw_w32(rtl8380_sds5_fiber_6275b
[2 * i
+ 1], rtl8380_sds5_fiber_6275b
[2 * i
]);
1112 while (rtl8380_sds_reset
[2 * i
]) {
1113 sw_w32(rtl8380_sds_reset
[2 * i
+ 1], rtl8380_sds_reset
[2 * i
]);
1118 while (rtl8380_sds_release_reset
[2 * i
]) {
1119 sw_w32(rtl8380_sds_release_reset
[2 * i
+ 1], rtl8380_sds_release_reset
[2 * i
]);
1123 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG
));
1124 sw_w32(sds_conf_value
, RTL838X_SDS_CFG_REG
);
1126 pr_info("Configuration of SERDES done\n");
1130 static int rtl8390_configure_serdes(struct phy_device
*phydev
)
1132 phydev_info(phydev
, "Detected internal RTL8390 SERDES\n");
1134 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1135 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0
+ 0x0a);
1137 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1138 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1139 * and FRE16_EEE_QUIET_FIB1G
1141 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0
+ 0xe0);
1146 static int rtl8214fc_phy_probe(struct phy_device
*phydev
)
1148 struct device
*dev
= &phydev
->mdio
.dev
;
1149 struct rtl838x_phy_priv
*priv
;
1150 int addr
= phydev
->mdio
.addr
;
1152 /* 839x has internal SerDes */
1153 if (soc_info
.id
== 0x8393)
1156 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1160 priv
->name
= "RTL8214FC";
1162 /* All base addresses of the PHYs start at multiples of 8 */
1164 /* Configuration must be done whil patching still possible */
1165 return rtl8380_configure_rtl8214fc(phydev
);
1170 static int rtl8214c_phy_probe(struct phy_device
*phydev
)
1172 struct device
*dev
= &phydev
->mdio
.dev
;
1173 struct rtl838x_phy_priv
*priv
;
1174 int addr
= phydev
->mdio
.addr
;
1176 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1180 priv
->name
= "RTL8214C";
1182 /* All base addresses of the PHYs start at multiples of 8 */
1184 /* Configuration must be done whil patching still possible */
1185 return rtl8380_configure_rtl8214c(phydev
);
1190 static int rtl8218b_ext_phy_probe(struct phy_device
*phydev
)
1192 struct device
*dev
= &phydev
->mdio
.dev
;
1193 struct rtl838x_phy_priv
*priv
;
1194 int addr
= phydev
->mdio
.addr
;
1196 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1200 priv
->name
= "RTL8218B (external)";
1202 /* All base addresses of the PHYs start at multiples of 8 */
1203 if (!(addr
% 8) && soc_info
.family
== RTL8380_FAMILY_ID
) {
1204 /* Configuration must be done while patching still possible */
1205 return rtl8380_configure_ext_rtl8218b(phydev
);
1210 static int rtl8218b_int_phy_probe(struct phy_device
*phydev
)
1212 struct device
*dev
= &phydev
->mdio
.dev
;
1213 struct rtl838x_phy_priv
*priv
;
1214 int addr
= phydev
->mdio
.addr
;
1216 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
1221 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1225 priv
->name
= "RTL8218B (internal)";
1227 /* All base addresses of the PHYs start at multiples of 8 */
1229 /* Configuration must be done while patching still possible */
1230 return rtl8380_configure_int_rtl8218b(phydev
);
1235 static int rtl838x_serdes_probe(struct phy_device
*phydev
)
1237 struct device
*dev
= &phydev
->mdio
.dev
;
1238 struct rtl838x_phy_priv
*priv
;
1239 int addr
= phydev
->mdio
.addr
;
1241 if (soc_info
.family
!= RTL8380_FAMILY_ID
)
1246 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1250 priv
->name
= "RTL8380 Serdes";
1252 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
1253 if (soc_info
.id
== 0x8380) {
1255 return rtl8380_configure_serdes(phydev
);
1261 static int rtl8393_serdes_probe(struct phy_device
*phydev
)
1263 struct device
*dev
= &phydev
->mdio
.dev
;
1264 struct rtl838x_phy_priv
*priv
;
1265 int addr
= phydev
->mdio
.addr
;
1267 pr_info("%s: id: %d\n", __func__
, addr
);
1268 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
1274 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1278 priv
->name
= "RTL8393 Serdes";
1279 return rtl8390_configure_serdes(phydev
);
1282 static int rtl8390_serdes_probe(struct phy_device
*phydev
)
1284 struct device
*dev
= &phydev
->mdio
.dev
;
1285 struct rtl838x_phy_priv
*priv
;
1286 int addr
= phydev
->mdio
.addr
;
1288 if (soc_info
.family
!= RTL8390_FAMILY_ID
)
1294 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1298 priv
->name
= "RTL8390 Serdes";
1299 return rtl8390_configure_generic(phydev
);
1302 static struct phy_driver rtl83xx_phy_driver
[] = {
1304 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C
),
1305 .name
= "Realtek RTL8214C",
1306 .features
= PHY_GBIT_FEATURES
,
1307 .match_phy_device
= rtl8214c_match_phy_device
,
1308 .probe
= rtl8214c_phy_probe
,
1309 .suspend
= genphy_suspend
,
1310 .resume
= genphy_resume
,
1311 .set_loopback
= genphy_loopback
,
1314 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
),
1315 .name
= "Realtek RTL8214FC",
1316 .features
= PHY_GBIT_FIBRE_FEATURES
,
1317 .match_phy_device
= rtl8214fc_match_phy_device
,
1318 .probe
= rtl8214fc_phy_probe
,
1319 .suspend
= genphy_suspend
,
1320 .resume
= genphy_resume
,
1321 .set_loopback
= genphy_loopback
,
1322 .read_mmd
= rtl8218b_read_mmd
,
1323 .write_mmd
= rtl8218b_write_mmd
,
1324 .set_port
= rtl8214fc_set_port
,
1325 .get_port
= rtl8214fc_get_port
,
1326 .set_eee
= rtl8214fc_set_eee
,
1327 .get_eee
= rtl8214fc_get_eee
,
1330 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E
),
1331 .name
= "Realtek RTL8218B (external)",
1332 .features
= PHY_GBIT_FEATURES
,
1333 .match_phy_device
= rtl8218b_ext_match_phy_device
,
1334 .probe
= rtl8218b_ext_phy_probe
,
1335 .suspend
= genphy_suspend
,
1336 .resume
= genphy_resume
,
1337 .set_loopback
= genphy_loopback
,
1338 .read_mmd
= rtl8218b_read_mmd
,
1339 .write_mmd
= rtl8218b_write_mmd
,
1340 .set_eee
= rtl8218b_set_eee
,
1341 .get_eee
= rtl8218b_get_eee
,
1344 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
1345 .name
= "Realtek RTL8218B (internal)",
1346 .features
= PHY_GBIT_FEATURES
,
1347 .probe
= rtl8218b_int_phy_probe
,
1348 .suspend
= genphy_suspend
,
1349 .resume
= genphy_resume
,
1350 .set_loopback
= genphy_loopback
,
1351 .read_mmd
= rtl8218b_read_mmd
,
1352 .write_mmd
= rtl8218b_write_mmd
,
1353 .set_eee
= rtl8218b_set_eee
,
1354 .get_eee
= rtl8218b_get_eee
,
1357 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I
),
1358 .name
= "Realtek RTL8380 SERDES",
1359 .features
= PHY_GBIT_FIBRE_FEATURES
,
1360 .probe
= rtl838x_serdes_probe
,
1361 .suspend
= genphy_suspend
,
1362 .resume
= genphy_resume
,
1363 .set_loopback
= genphy_loopback
,
1364 .read_mmd
= rtl8218b_read_mmd
,
1365 .write_mmd
= rtl8218b_write_mmd
,
1366 .read_status
= rtl8380_read_status
,
1369 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I
),
1370 .name
= "Realtek RTL8393 SERDES",
1371 .features
= PHY_GBIT_FIBRE_FEATURES
,
1372 .probe
= rtl8393_serdes_probe
,
1373 .suspend
= genphy_suspend
,
1374 .resume
= genphy_resume
,
1375 .set_loopback
= genphy_loopback
,
1376 .read_status
= rtl8393_read_status
,
1379 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC
),
1380 .name
= "Realtek RTL8390 Generic",
1381 .features
= PHY_GBIT_FIBRE_FEATURES
,
1382 .probe
= rtl8390_serdes_probe
,
1383 .suspend
= genphy_suspend
,
1384 .resume
= genphy_resume
,
1385 .set_loopback
= genphy_loopback
,
1389 module_phy_driver(rtl83xx_phy_driver
);
1391 static struct mdio_device_id __maybe_unused rtl83xx_tbl
[] = {
1392 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC
) },
1396 MODULE_DEVICE_TABLE(mdio
, rtl83xx_tbl
);
1398 MODULE_AUTHOR("B. Koblitz");
1399 MODULE_DESCRIPTION("RTL83xx PHY driver");
1400 MODULE_LICENSE("GPL");