target/linux/rockchip/patches-6.1/013-v6.4-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch

   1 From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Sat, 18 Mar 2023 16:37:43 +0800
   4 Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C
   5
   6 FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
   7
   8 Specification:
   9 - Rockchip RK3568
  10 - 1/4GB LPDDR4X RAM
  11 - 8/32GB eMMC
  12 - SD card slot
  13 - M.2 Connector
  14 - 2x USB 3.0 Port
  15 - 2x 2500 Base-T (PCIe, r8125)
  16 - HDMI 2.0
  17 - MIPI DSI/CSI
  18 - USB Type C 5V
  19
  20 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  21 Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com
  22 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  23 ---
  24  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
  25  .../boot/dts/rockchip/rk3568-nanopi-r5c.dts   | 112 ++++++++++++++++++
  26  2 files changed, 113 insertions(+)
  27  create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
  28
  29 --- a/arch/arm64/boot/dts/rockchip/Makefile
  30 +++ b/arch/arm64/boot/dts/rockchip/Makefile
  31 @@ -74,5 +74,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
  32  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
  33  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
  34  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
  35 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
  36  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
  37  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
  38 --- /dev/null
  39 +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
  40 @@ -0,0 +1,112 @@
  41 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  42 +/*
  43 + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
  44 + * (http://www.friendlyelec.com)
  45 + *
  46 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
  47 + */
  48 +
  49 +/dts-v1/;
  50 +#include "rk3568-nanopi-r5s.dtsi"
  51 +
  52 +/ {
  53 +       model = "FriendlyElec NanoPi R5C";
  54 +       compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
  55 +
  56 +       gpio-keys {
  57 +               compatible = "gpio-keys";
  58 +               pinctrl-names = "default";
  59 +               pinctrl-0 = <&reset_button_pin>;
  60 +
  61 +               button-reset {
  62 +                       debounce-interval = <50>;
  63 +                       gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
  64 +                       label = "reset";
  65 +                       linux,code = <KEY_RESTART>;
  66 +               };
  67 +       };
  68 +
  69 +       gpio-leds {
  70 +               compatible = "gpio-leds";
  71 +               pinctrl-names = "default";
  72 +               pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
  73 +
  74 +               led-lan {
  75 +                       color = <LED_COLOR_ID_GREEN>;
  76 +                       function = LED_FUNCTION_LAN;
  77 +                       gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
  78 +               };
  79 +
  80 +               power_led: led-power {
  81 +                       color = <LED_COLOR_ID_RED>;
  82 +                       function = LED_FUNCTION_POWER;
  83 +                       linux,default-trigger = "heartbeat";
  84 +                       gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
  85 +               };
  86 +
  87 +               led-wan {
  88 +                       color = <LED_COLOR_ID_GREEN>;
  89 +                       function = LED_FUNCTION_WAN;
  90 +                       gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
  91 +               };
  92 +
  93 +               led-wlan {
  94 +                       color = <LED_COLOR_ID_GREEN>;
  95 +                       function = LED_FUNCTION_WLAN;
  96 +                       gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
  97 +               };
  98 +       };
  99 +};
 100 +
 101 +&pcie2x1 {
 102 +       pinctrl-names = "default";
 103 +       pinctrl-0 = <&pcie20_reset_pin>;
 104 +       reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
 105 +       status = "okay";
 106 +};
 107 +
 108 +&pcie3x1 {
 109 +       num-lanes = <1>;
 110 +       reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
 111 +       vpcie3v3-supply = <&vcc3v3_pcie>;
 112 +       status = "okay";
 113 +};
 114 +
 115 +&pcie3x2 {
 116 +       num-lanes = <1>;
 117 +       reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
 118 +       vpcie3v3-supply = <&vcc3v3_pcie>;
 119 +       status = "okay";
 120 +};
 121 +
 122 +&pinctrl {
 123 +       gpio-leds {
 124 +               lan_led_pin: lan-led-pin {
 125 +                       rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 126 +               };
 127 +
 128 +               power_led_pin: power-led-pin {
 129 +                       rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 130 +               };
 131 +
 132 +               wan_led_pin: wan-led-pin {
 133 +                       rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 134 +               };
 135 +
 136 +               wlan_led_pin: wlan-led-pin {
 137 +                       rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 138 +               };
 139 +       };
 140 +
 141 +       pcie {
 142 +               pcie20_reset_pin: pcie20-reset-pin {
 143 +                       rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
 144 +               };
 145 +       };
 146 +
 147 +       rockchip-key {
 148 +               reset_button_pin: reset-button-pin {
 149 +                       rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
 150 +               };
 151 +       };
 152 +};