target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   4  * Copyright (C) 2020 B. Koblitz
   5  */
   6 #ifndef _MACH_RTL838X_H_
   7 #define _MACH_RTL838X_H_
   8
   9 /*
  10  * Register access macros
  11  */
  12
  13 #define RTL838X_SW_BASE         ((volatile void *) 0xBB000000)
  14
  15 #define rtl838x_r32(reg)        __raw_readl(reg)
  16 #define rtl838x_w32(val, reg)   __raw_writel(val, reg)
  17 #define rtl838x_w32_mask(clear, set, reg) rtl838x_w32((rtl838x_r32(reg) & ~(clear)) | (set), reg)
  18
  19 #define sw_r32(reg)             __raw_readl(RTL838X_SW_BASE + reg)
  20 #define sw_w32(val, reg)        __raw_writel(val, RTL838X_SW_BASE + reg)
  21 #define sw_w32_mask(clear, set, reg)    \
  22                                 sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
  23
  24 #define sw_r64(reg)             ((((u64)__raw_readl(RTL838X_SW_BASE + reg)) << 32) | \
  25                                 __raw_readl(RTL838X_SW_BASE + reg + 4))
  26
  27 #define sw_w64(val, reg)        do { \
  28                                         __raw_writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
  29                                         __raw_writel((u32)((val) & 0xffffffff), \
  30                                                         RTL838X_SW_BASE + reg + 4); \
  31                                 } while (0)
  32
  33 /*
  34  * SPRAM
  35  */
  36 #define RTL838X_ISPRAM_BASE     0x0
  37 #define RTL838X_DSPRAM_BASE     0x0
  38
  39 /*
  40  * IRQ Controller
  41  */
  42 #define RTL838X_IRQ_CPU_BASE    0
  43 #define RTL838X_IRQ_CPU_NUM     8
  44 #define RTL838X_IRQ_ICTL_BASE   (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
  45 #define RTL838X_IRQ_ICTL_NUM    32
  46
  47 /*
  48  * MIPS32R2 counter
  49  */
  50 #define RTL838X_COMPARE_IRQ     (RTL838X_IRQ_CPU_BASE + 7)
  51
  52 /*
  53  *  ICTL
  54  *  Base address 0xb8003000UL
  55  */
  56 #define RTL838X_ICTL1_IRQ       (RTL838X_IRQ_CPU_BASE + 2)
  57 #define RTL838X_ICTL2_IRQ       (RTL838X_IRQ_CPU_BASE + 3)
  58 #define RTL838X_ICTL3_IRQ       (RTL838X_IRQ_CPU_BASE + 4)
  59 #define RTL838X_ICTL4_IRQ       (RTL838X_IRQ_CPU_BASE + 5)
  60 #define RTL838X_ICTL5_IRQ       (RTL838X_IRQ_CPU_BASE + 6)
  61
  62 #define GIMR                    (0x00)
  63 #define UART0_IE                (1 << 31)
  64 #define UART1_IE                (1 << 30)
  65 #define TC0_IE                  (1 << 29)
  66 #define TC1_IE                  (1 << 28)
  67 #define OCPTO_IE                (1 << 27)
  68 #define HLXTO_IE                (1 << 26)
  69 #define SLXTO_IE                (1 << 25)
  70 #define NIC_IE                  (1 << 24)
  71 #define GPIO_ABCD_IE            (1 << 23)
  72 #define GPIO_EFGH_IE            (1 << 22)
  73 #define RTC_IE                  (1 << 21)
  74 #define WDT_IP1_IE              (1 << 19)
  75 #define WDT_IP2_IE              (1 << 18)
  76
  77 #define GISR                    (0x04)
  78 #define UART0_IP                (1 << 31)
  79 #define UART1_IP                (1 << 30)
  80 #define TC0_IP                  (1 << 29)
  81 #define TC1_IP                  (1 << 28)
  82 #define OCPTO_IP                (1 << 27)
  83 #define HLXTO_IP                (1 << 26)
  84 #define SLXTO_IP                (1 << 25)
  85 #define NIC_IP                  (1 << 24)
  86 #define GPIO_ABCD_IP            (1 << 23)
  87 #define GPIO_EFGH_IP            (1 << 22)
  88 #define RTC_IP                  (1 << 21)
  89 #define WDT_IP1_IP              (1 << 19)
  90 #define WDT_IP2_IP              (1 << 18)
  91
  92 #define IRR0                    (0x08)
  93 #define IRR0_SETTING            ((UART0_RS  << 28) | \
  94                                  (UART1_RS  << 24) | \
  95                                  (TC0_RS    << 20) | \
  96                                  (TC1_RS    << 16) | \
  97                                  (OCPTO_RS  << 12) | \
  98                                  (HLXTO_RS  << 8)  | \
  99                                  (SLXTO_RS  << 4)  | \
 100                                  (NIC_RS    << 0)    \
 101                                 )
 102
 103 #define IRR1                    (0x0c)
 104
 105 #define IRR1_SETTING            ((GPIO_ABCD_RS << 28) | \
 106                                  (GPIO_EFGH_RS << 24) | \
 107                                  (RTC_RS       << 20) | \
 108                                  (SWCORE_RS    << 16)   \
 109                                 )
 110
 111 #define IRR2                    (0x10)
 112 #define IRR2_SETTING            0
 113
 114 #define IRR3                    (0x14)
 115 #define IRR3_SETTING            0
 116
 117 /* Interrupt Routing Selection */
 118 #define UART0_RS                2
 119 #define UART1_RS                1
 120 #define TC0_RS                  5
 121 #define TC1_RS                  1
 122 #define OCPTO_RS                1
 123 #define HLXTO_RS                1
 124 #define SLXTO_RS                1
 125 #define NIC_RS                  4
 126 #define GPIO_ABCD_RS            4
 127 #define GPIO_EFGH_RS            4
 128 #define RTC_RS                  4
 129 #define SWCORE_RS               3
 130 #define WDT_IP1_RS              4
 131 #define WDT_IP2_RS              5
 132
 133 /* Interrupt IRQ Assignments */
 134 #define UART0_IRQ               31
 135 #define UART1_IRQ               30
 136 #define TC0_IRQ                 29
 137 #define TC1_IRQ                 28
 138 #define OCPTO_IRQ               27
 139 #define HLXTO_IRQ               26
 140 #define SLXTO_IRQ               25
 141 #define NIC_IRQ                 24
 142 #define GPIO_ABCD_IRQ           23
 143 #define GPIO_EFGH_IRQ           22
 144 #define RTC_IRQ                 21
 145 #define SWCORE_IRQ              20
 146 #define WDT_IP1_IRQ             19
 147 #define WDT_IP2_IRQ             18
 148
 149 #define SYSTEM_FREQ             200000000
 150 #define RTL838X_UART0_BASE      ((volatile void *)(0xb8002000UL))
 151 #define RTL838X_UART0_BAUD      38400  /* ex. 19200 or 38400 or 57600 or 115200 */
 152 #define RTL838X_UART0_FREQ      (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
 153 #define RTL838X_UART0_MAPBASE   0x18002000UL
 154 #define RTL838X_UART0_MAPSIZE   0x100
 155 #define RTL838X_UART0_IRQ       UART0_IRQ
 156
 157 #define RTL838X_UART1_BASE      ((volatile void *)(0xb8002100UL))
 158 #define RTL838X_UART1_BAUD      38400  /* ex. 19200 or 38400 or 57600 or 115200 */
 159 #define RTL838X_UART1_FREQ      (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
 160 #define RTL838X_UART1_MAPBASE   0x18002100UL
 161 #define RTL838X_UART1_MAPSIZE   0x100
 162 #define RTL838X_UART1_IRQ       UART1_IRQ
 163
 164 #define UART0_RBR               (RTL838X_UART0_BASE + 0x000)
 165 #define UART0_THR               (RTL838X_UART0_BASE + 0x000)
 166 #define UART0_DLL               (RTL838X_UART0_BASE + 0x000)
 167 #define UART0_IER               (RTL838X_UART0_BASE + 0x004)
 168 #define UART0_DLM               (RTL838X_UART0_BASE + 0x004)
 169 #define UART0_IIR               (RTL838X_UART0_BASE + 0x008)
 170 #define UART0_FCR               (RTL838X_UART0_BASE + 0x008)
 171 #define UART0_LCR               (RTL838X_UART0_BASE + 0x00C)
 172 #define UART0_MCR               (RTL838X_UART0_BASE + 0x010)
 173 #define UART0_LSR               (RTL838X_UART0_BASE + 0x014)
 174
 175 #define UART1_RBR               (RTL838X_UART1_BASE + 0x000)
 176 #define UART1_THR               (RTL838X_UART1_BASE + 0x000)
 177 #define UART1_DLL               (RTL838X_UART1_BASE + 0x000)
 178 #define UART1_IER               (RTL838X_UART1_BASE + 0x004)
 179 #define UART1_DLM               (RTL838X_UART1_BASE + 0x004)
 180 #define UART1_IIR               (RTL838X_UART1_BASE + 0x008)
 181 #define UART1_FCR               (RTL838X_UART1_BASE + 0x008)
 182    #define FCR_EN               0x01
 183    #define FCR_RXRST            0x02
 184    #define XRST                 0x02
 185    #define FCR_TXRST            0x04
 186    #define TXRST                0x04
 187    #define FCR_DMA              0x08
 188    #define FCR_RTRG             0xC0
 189    #define CHAR_TRIGGER_01      0x00
 190    #define CHAR_TRIGGER_04      0x40
 191    #define CHAR_TRIGGER_08      0x80
 192    #define CHAR_TRIGGER_14      0xC0
 193 #define UART1_LCR               (RTL838X_UART1_BASE + 0x00C)
 194    #define LCR_WLN              0x03
 195    #define CHAR_LEN_5           0x00
 196    #define CHAR_LEN_6           0x01
 197    #define CHAR_LEN_7           0x02
 198    #define CHAR_LEN_8           0x03
 199    #define LCR_STB              0x04
 200    #define ONE_STOP             0x00
 201    #define TWO_STOP             0x04
 202    #define LCR_PEN              0x08
 203    #define PARITY_ENABLE        0x01
 204    #define PARITY_DISABLE       0x00
 205    #define LCR_EPS              0x30
 206    #define PARITY_ODD           0x00
 207    #define PARITY_EVEN          0x10
 208    #define PARITY_MARK          0x20
 209    #define PARITY_SPACE         0x30
 210    #define LCR_BRK              0x40
 211    #define LCR_DLAB             0x80
 212    #define DLAB                 0x80
 213 #define UART1_MCR               (RTL838X_UART1_BASE + 0x010)
 214 #define UART1_LSR               (RTL838X_UART1_BASE + 0x014)
 215    #define LSR_DR               0x01
 216    #define RxCHAR_AVAIL         0x01
 217    #define LSR_OE               0x02
 218    #define LSR_PE               0x04
 219    #define LSR_FE               0x08
 220    #define LSR_BI               0x10
 221    #define LSR_THRE             0x20
 222    #define TxCHAR_AVAIL         0x00
 223    #define TxCHAR_EMPTY         0x20
 224    #define LSR_TEMT             0x40
 225    #define LSR_RFE              0x80
 226
 227 /*
 228  *  Timer/counter for 8390/80/28 TC & MP chip
 229  */
 230 #define RTL838X_TIMER0_BASE     ((volatile void *)(0xb8003100UL))
 231 #define RTL838X_TIMER0_IRQ      RTL838X_TC0_EXT_IRQ
 232
 233 #define RTL8390TC_TC1DATA       (RTL838X_TIMER0_BASE + 0x04)
 234 #define RTL8390TC_TCD_OFFSET    8
 235 #define RTL8390TC_TC0CNT        (RTL838X_TIMER0_BASE + 0x08)
 236 #define RTL8390TC_TC1CNT        (RTL838X_TIMER0_BASE + 0x0C)
 237 #define RTL8390TC_TCCNR         (RTL838X_TIMER0_BASE + 0x10)
 238 #define RTL8390TC_TC0EN         (1 << 31)
 239 #define RTL8390TC_TC0MODE_TIMER (1 << 30)
 240 #define RTL8390TC_TC1EN         (1 << 29)
 241 #define RTL8390TC_TC1MODE_TIMER (1 << 28)
 242 #define RTL8390TC_TCIR          (RTL838X_TIMER0_BASE + 0x14)
 243 #define RTL8390TC_TC0IE         (1 << 31)
 244 #define RTL8390TC_TC1IE         (1 << 30)
 245 #define RTL8390TC_TC0IP         (1 << 29)
 246 #define RTL8390TC_TC1IP         (1 << 28)
 247 #define RTL8390TC_CDBR          (RTL838X_TIMER0_BASE + 0x18)
 248 #define RTL8390TC_DIVF_OFFSET   16
 249 #define RTL8390TC_WDTCNR        (RTL838X_TIMER0_BASE + 0x1C)
 250
 251 #define RTL8390MP_TC1DATA       (RTL838X_TIMER0_BASE + 0x10)
 252 #define RTL8390MP_TC0CNT        (RTL838X_TIMER0_BASE + 0x04)
 253 #define RTL8390MP_TC1CNT        (RTL838X_TIMER0_BASE + 0x14)
 254 #define RTL8390MP_TC0CTL        (RTL838X_TIMER0_BASE + 0x08)
 255 #define RTL8390MP_TC1CTL        (RTL838X_TIMER0_BASE + 0x18)
 256 #define RTL8390MP_TCEN          (1 << 28)
 257 #define RTL8390MP_TCMODE_TIMER  (1 << 24)
 258 #define RTL8390MP_TCDIV_FACTOR  (0xFFFF << 0)
 259 #define RTL8390MP_TC0INT        (RTL838X_TIMER0_BASE + 0xC)
 260 #define RTL8390MP_TC1INT        (RTL838X_TIMER0_BASE + 0x1C)
 261 #define RTL8390MP_TCIE          (1 << 20)
 262 #define RTL8390MP_TCIP          (1 << 16)
 263 #define RTL8390MP_WDTCNR        (RTL838X_TIMER0_BASE + 0x50)
 264
 265 #define RTL8380MP_TC0DATA       (RTL838X_TIMER0_BASE + 0x00)
 266 #define RTL8380MP_TC1DATA       (RTL838X_TIMER0_BASE + 0x10)
 267 #define RTL8380MP_TC0CNT        (RTL838X_TIMER0_BASE + 0x04)
 268 #define RTL8380MP_TC1CNT        (RTL838X_TIMER0_BASE + 0x14)
 269 #define RTL8380MP_TC0CTL        (RTL838X_TIMER0_BASE + 0x08)
 270 #define RTL8380MP_TC1CTL        (RTL838X_TIMER0_BASE + 0x18)
 271 #define RTL8380MP_TCEN          (1 << 28)
 272 #define RTL8380MP_TCMODE_TIMER  (1 << 24)
 273 #define RTL8380MP_TCDIV_FACTOR  (0xFFFF << 0)
 274 #define RTL8380MP_TC0INT        (RTL838X_TIMER0_BASE + 0xC)
 275 #define RTL8380MP_TC1INT        (RTL838X_TIMER0_BASE + 0x1C)
 276 #define RTL8380MP_TCIE          (1 << 20)
 277 #define RTL8380MP_TCIP          (1 << 16)
 278 #define RTL8380MP_WDTCNR        (RTL838X_TIMER0_BASE + 0x50)
 279
 280 #define DIVISOR_RTL8390         55
 281 #define DIVISOR_RTL8380         2500
 282 #define DIVISOR_MAX             16834
 283
 284 /*
 285  * Memory Controller
 286  */
 287 #define MC_MCR                  0xB8001000
 288 #define MC_MCR_VAL              0x00000000
 289
 290 #define MC_DCR                  0xB8001004
 291 #define MC_DCR0_VAL             0x54480000
 292
 293 #define MC_DTCR                 0xB8001008
 294 #define MC_DTCR_VAL             0xFFFF05C0
 295
 296 /*
 297  * GPIO
 298  */
 299 #define GPIO_CTRL_REG_BASE              ((volatile void *) 0xb8003500)
 300 #define RTL838X_GPIO_PABC_CNR           (GPIO_CTRL_REG_BASE + 0x0)
 301 #define RTL838X_GPIO_PABC_TYPE          (GPIO_CTRL_REG_BASE + 0x04)
 302 #define RTL838X_GPIO_PABC_DIR           (GPIO_CTRL_REG_BASE + 0x8)
 303 #define RTL838X_GPIO_PABC_DATA          (GPIO_CTRL_REG_BASE + 0xc)
 304 #define RTL838X_GPIO_PABC_ISR           (GPIO_CTRL_REG_BASE + 0x10)
 305 #define RTL838X_GPIO_PAB_IMR            (GPIO_CTRL_REG_BASE + 0x14)
 306 #define RTL838X_GPIO_PC_IMR             (GPIO_CTRL_REG_BASE + 0x18)
 307
 308 #define RTL838X_MODEL_NAME_INFO         (0x00D4)
 309 #define RTL839X_MODEL_NAME_INFO         (0x0FF0)
 310 #define RTL838X_LED_GLB_CTRL            (0xA000)
 311 #define RTL839X_LED_GLB_CTRL            (0x00E4)
 312 #define RTL838X_EXT_GPIO_DIR_0          (0xA08C)
 313 #define RTL838X_EXT_GPIO_DIR_1          (0xA090)
 314 #define RTL838X_EXT_GPIO_DATA_0         (0xA094)
 315 #define RTL838X_EXT_GPIO_DATA_1         (0xA098)
 316 #define RTL838X_EXT_GPIO_INDRT_ACCESS   (0xA09C)
 317 #define RTL838X_EXTRA_GPIO_CTRL         (0xA0E0)
 318 #define RTL838X_EXTRA_GPIO_DIR_0        (0xA0E4)
 319 #define RTL838X_EXTRA_GPIO_DIR_1        (0xA0E8)
 320 #define RTL838X_EXTRA_GPIO_DATA_0       (0xA0EC)
 321 #define RTL838X_EXTRA_GPIO_DATA_1       (0xA0F0)
 322 #define RTL838X_DMY_REG5                (0x0144)
 323 #define RTL838X_EXTRA_GPIO_CTRL         (0xA0E0)
 324
 325 #define RTL838X_GMII_INTF_SEL           (0x1000)
 326 #define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010)
 327
 328 #define RTL838X_GPIO_A7         31
 329 #define RTL838X_GPIO_A6         30
 330 #define RTL838X_GPIO_A5         29
 331 #define RTL838X_GPIO_A4         28
 332 #define RTL838X_GPIO_A3         27
 333 #define RTL838X_GPIO_A2         26
 334 #define RTL838X_GPIO_A1         25
 335 #define RTL838X_GPIO_A0         24
 336 #define RTL838X_GPIO_B7         23
 337 #define RTL838X_GPIO_B6         22
 338 #define RTL838X_GPIO_B5         21
 339 #define RTL838X_GPIO_B4         20
 340 #define RTL838X_GPIO_B3         19
 341 #define RTL838X_GPIO_B2         18
 342 #define RTL838X_GPIO_B1         17
 343 #define RTL838X_GPIO_B0         16
 344 #define RTL838X_GPIO_C7         15
 345 #define RTL838X_GPIO_C6         14
 346 #define RTL838X_GPIO_C5         13
 347 #define RTL838X_GPIO_C4         12
 348 #define RTL838X_GPIO_C3         11
 349 #define RTL838X_GPIO_C2         10
 350 #define RTL838X_GPIO_C1         9
 351 #define RTL838X_GPIO_C0         8
 352
 353 #define RTL838X_INT_RW_CTRL             (0x0058)
 354 #define RTL838X_EXT_VERSION             (0x00D0)
 355 #define RTL838X_PLL_CML_CTRL            (0x0FF8)
 356 #define RTL838X_STRAP_DBG               (0x100C)
 357
 358 /*
 359  * Reset
 360  */
 361 #define RGCR                            (0x1E70)
 362 #define RTL839X_RST_GLB_CTRL            (0x0014)
 363 #define RTL838X_RST_GLB_CTRL_1          (0x0040)
 364
 365 /* LED control by switch */
 366 #define RTL838X_LED_MODE_SEL            (0x1004)
 367 #define RTL838X_LED_MODE_CTRL           (0xA004)
 368 #define RTL838X_LED_P_EN_CTRL           (0xA008)
 369
 370 /* LED control by software */
 371 #define RTL838X_LED_SW_CTRL             (0xA00C)
 372 #define RTL838X_LED0_SW_P_EN_CTRL       (0xA010)
 373 #define RTL838X_LED1_SW_P_EN_CTRL       (0xA014)
 374 #define RTL838X_LED2_SW_P_EN_CTRL       (0xA018)
 375 #define RTL838X_LED_SW_P_CTRL(p)        (0xA01C + ((p) << 2))
 376
 377 #define RTL839X_MAC_EFUSE_CTRL          (0x02ac)
 378
 379 /*
 380  * MDIO via Realtek's SMI interface
 381  */
 382 #define RTL838X_SMI_GLB_CTRL            (0xa100)
 383 #define RTL838X_SMI_ACCESS_PHY_CTRL_0   (0xa1b8)
 384 #define RTL838X_SMI_ACCESS_PHY_CTRL_1   (0xa1bc)
 385 #define RTL838X_SMI_ACCESS_PHY_CTRL_2   (0xa1c0)
 386 #define RTL838X_SMI_ACCESS_PHY_CTRL_3   (0xa1c4)
 387 #define RTL838X_SMI_PORT0_5_ADDR_CTRL   (0xa1c8)
 388 #define RTL838X_SMI_POLL_CTRL           (0xa17c)
 389
 390 #define RTL839X_SMI_GLB_CTRL            (0x03f8)
 391 #define RTL839X_SMI_PORT_POLLING_CTRL   (0x03fc)
 392 #define RTL839X_PHYREG_ACCESS_CTRL      (0x03DC)
 393 #define RTL839X_PHYREG_CTRL             (0x03E0)
 394 #define RTL839X_PHYREG_PORT_CTRL(p)     (0x03E4 + ((p >> 5) << 2))
 395 #define RTL839X_PHYREG_DATA_CTRL        (0x03F0)
 396
 397 /*
 398  * Switch interrupts
 399  */
 400 #define RTL838X_IMR_GLB                 (0x1100)
 401 #define RTL838X_IMR_PORT_LINK_STS_CHG   (0x1104)
 402 #define RTL838X_ISR_GLB_SRC             (0x1148)
 403 #define RTL838X_ISR_PORT_LINK_STS_CHG   (0x114C)
 404 #define RTL839X_IMR_GLB                 (0x0064)
 405 #define RTL839X_IMR_PORT_LINK_STS_CHG   (0x0068)
 406 #define RTL839X_ISR_GLB_SRC             (0x009c)
 407 #define RTL839X_ISR_PORT_LINK_STS_CHG   (0x00a0)
 408
 409 /* Definition of family IDs */
 410 #define RTL8389_FAMILY_ID   (0x8389)
 411 #define RTL8328_FAMILY_ID   (0x8328)
 412 #define RTL8390_FAMILY_ID   (0x8390)
 413 #define RTL8350_FAMILY_ID   (0x8350)
 414 #define RTL8380_FAMILY_ID   (0x8380)
 415 #define RTL8330_FAMILY_ID   (0x8330)
 416
 417 struct rtl838x_soc_info {
 418         unsigned char *name;
 419         unsigned int id;
 420         unsigned int family;
 421         unsigned char *compatible;
 422         volatile void *sw_base;
 423         volatile void *icu_base;
 424 };
 425
 426 void rtl838x_soc_detect(struct rtl838x_soc_info *i);
 427
 428 #endif   /* _MACH_RTL838X_H_ */