1 // SPDX-License-Identifier: GPL-2.0-only
3 * Realtek RTL838X architecture specific IRQ handling
5 * Copyright (C) 2020 B. Koblitz
6 * based on the original BSP
7 * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_address.h>
17 #include <linux/spinlock.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
21 #include <mach-rtl838x.h>
23 extern struct rtl838x_soc_info soc_info
;
25 #define icu_r32(reg) rtl838x_r32(soc_info.icu_base + reg)
26 #define icu_w32(val, reg) rtl838x_w32(val, soc_info.icu_base + reg)
27 #define icu_w32_mask(clear, set, reg) rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
29 static DEFINE_RAW_SPINLOCK(irq_lock
);
31 extern irqreturn_t
c0_compare_interrupt(int irq
, void *dev_id
);
34 static void rtl838x_ictl_enable_irq(struct irq_data
*i
)
38 raw_spin_lock_irqsave(&irq_lock
, flags
);
39 icu_w32_mask(0, 1 << i
->irq
, GIMR
);
40 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
43 static void rtl838x_ictl_disable_irq(struct irq_data
*i
)
47 raw_spin_lock_irqsave(&irq_lock
, flags
);
48 icu_w32_mask(1 << i
->irq
, 0, GIMR
);
49 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
52 static void rtl838x_ictl_eoi_irq(struct irq_data
*i
)
56 raw_spin_lock_irqsave(&irq_lock
, flags
);
57 icu_w32_mask(0, 1 << i
->irq
, GIMR
);
58 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
61 static struct irq_chip rtl838x_ictl_irq
= {
63 .irq_enable
= rtl838x_ictl_enable_irq
,
64 .irq_disable
= rtl838x_ictl_disable_irq
,
65 .irq_ack
= rtl838x_ictl_disable_irq
,
66 .irq_mask
= rtl838x_ictl_disable_irq
,
67 .irq_unmask
= rtl838x_ictl_enable_irq
,
68 .irq_eoi
= rtl838x_ictl_eoi_irq
,
72 * RTL8390/80/28 Interrupt Scheme
75 * -------- ------- -------
88 asmlinkage
void plat_irq_dispatch(void)
90 unsigned int pending
, ext_int
;
92 pending
= read_c0_cause();
94 if (pending
& CAUSEF_IP7
) {
95 c0_compare_interrupt(7, NULL
);
96 } else if (pending
& CAUSEF_IP6
) {
98 } else if (pending
& CAUSEF_IP5
) {
99 ext_int
= icu_r32(GIMR
) & icu_r32(GISR
);
100 if (ext_int
& NIC_IP
)
102 else if (ext_int
& GPIO_ABCD_IP
)
103 do_IRQ(GPIO_ABCD_IRQ
);
104 else if ((ext_int
& GPIO_EFGH_IP
) && (soc_info
.family
== RTL8328_FAMILY_ID
))
105 do_IRQ(GPIO_EFGH_IRQ
);
107 spurious_interrupt();
108 } else if (pending
& CAUSEF_IP4
) {
110 } else if (pending
& CAUSEF_IP3
) {
112 } else if (pending
& CAUSEF_IP2
) {
113 ext_int
= icu_r32(GIMR
) & icu_r32(GISR
);
114 if (ext_int
& TC1_IP
)
116 else if (ext_int
& UART1_IP
)
119 spurious_interrupt();
121 spurious_interrupt();
125 static int intc_map(struct irq_domain
*d
, unsigned int irq
, irq_hw_number_t hw
)
127 irq_set_chip_and_handler(hw
, &rtl838x_ictl_irq
, handle_level_irq
);
132 static const struct irq_domain_ops irq_domain_ops
= {
133 .xlate
= irq_domain_xlate_onecell
,
137 int __init
icu_of_init(struct device_node
*node
, struct device_node
*parent
)
140 struct irq_domain
*domain
;
143 pr_info("Found Interrupt controller: %s (%s)\n", node
->name
, node
->full_name
);
144 if (of_address_to_resource(node
, 0, &res
))
145 panic("Failed to get icu memory range");
147 if (!request_mem_region(res
.start
, resource_size(&res
), res
.name
))
148 pr_err("Failed to request icu memory\n");
150 soc_info
.icu_base
= ioremap(res
.start
, resource_size(&res
));
151 pr_info("ICU Memory: %08x\n", (u32
)soc_info
.icu_base
);
155 domain
= irq_domain_add_simple(node
, 32, 0, &irq_domain_ops
, NULL
);
157 /* Setup all external HW irqs */
158 for (i
= 8; i
< RTL838X_IRQ_ICTL_NUM
; i
++) {
159 irq_domain_associate(domain
, i
, i
);
160 irq_set_chip_and_handler(RTL838X_IRQ_ICTL_BASE
+ i
,
161 &rtl838x_ictl_irq
, handle_level_irq
);
164 if (request_irq(RTL838X_ICTL1_IRQ
, no_action
, IRQF_NO_THREAD
,
165 "IRQ cascade 1", NULL
)) {
166 pr_err("request_irq() cascade 1 for irq %d failed\n", RTL838X_ICTL1_IRQ
);
168 if (request_irq(RTL838X_ICTL2_IRQ
, no_action
, IRQF_NO_THREAD
,
169 "IRQ cascade 2", NULL
)) {
170 pr_err("request_irq() cascade 2 for irq %d failed\n", RTL838X_ICTL2_IRQ
);
172 if (request_irq(RTL838X_ICTL3_IRQ
, no_action
, IRQF_NO_THREAD
,
173 "IRQ cascade 3", NULL
)) {
174 pr_err("request_irq() cascade 3 for irq %d failed\n", RTL838X_ICTL3_IRQ
);
176 if (request_irq(RTL838X_ICTL4_IRQ
, no_action
, IRQF_NO_THREAD
,
177 "IRQ cascade 4", NULL
)) {
178 pr_err("request_irq() cascade 4 for irq %d failed\n", RTL838X_ICTL4_IRQ
);
180 if (request_irq(RTL838X_ICTL5_IRQ
, no_action
, IRQF_NO_THREAD
,
181 "IRQ cascade 5", NULL
)) {
182 pr_err("request_irq() cascade 5 for irq %d failed\n", RTL838X_ICTL5_IRQ
);
185 /* Set up interrupt routing scheme */
186 icu_w32(IRR0_SETTING
, IRR0
);
187 if (soc_info
.family
== RTL8380_FAMILY_ID
)
188 icu_w32(IRR1_SETTING_RTL838X
, IRR1
);
190 icu_w32(IRR1_SETTING_RTL839X
, IRR1
);
191 icu_w32(IRR2_SETTING
, IRR2
);
192 icu_w32(IRR3_SETTING
, IRR3
);
194 /* Enable timer0 and uart0 interrupts */
195 icu_w32(TC0_IE
| UART0_IE
, GIMR
);
199 void __init
arch_init_irq(void)
201 /* do board-specific irq initialization */
205 IRQCHIP_DECLARE(mips_cpu_intc
, "rtl838x,icu", icu_of_init
);