target/linux/rtl838x/files-5.4/arch/mips/rtl838x/irq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Realtek RTL838X architecture specific IRQ handling
   4  *
   5  * Copyright  (C) 2020 B. Koblitz
   6  * based on the original BSP
   7  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   8  *
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irqchip.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_address.h>
  17 #include <linux/spinlock.h>
  18
  19 #include <asm/irq_cpu.h>
  20 #include <asm/mipsregs.h>
  21 #include <mach-rtl838x.h>
  22
  23 extern struct rtl838x_soc_info soc_info;
  24
  25 #define icu_r32(reg)                    rtl838x_r32(soc_info.icu_base + reg)
  26 #define icu_w32(val, reg)               rtl838x_w32(val, soc_info.icu_base + reg)
  27 #define icu_w32_mask(clear, set, reg)   rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
  28
  29 static DEFINE_RAW_SPINLOCK(irq_lock);
  30
  31 extern irqreturn_t c0_compare_interrupt(int irq, void *dev_id);
  32 unsigned int rtl838x_ictl_irq_dispatch1(void);
  33 unsigned int rtl838x_ictl_irq_dispatch2(void);
  34 unsigned int rtl838x_ictl_irq_dispatch3(void);
  35 unsigned int rtl838x_ictl_irq_dispatch4(void);
  36 unsigned int rtl838x_ictl_irq_dispatch5(void);
  37
  38 static struct irqaction irq_cascade1 = {
  39         .handler = no_action,
  40         .name = "RTL838X IRQ cascade1",
  41 };
  42
  43 static struct irqaction irq_cascade2 = {
  44         .handler = no_action,
  45         .name = "RTL838X IRQ cascade2",
  46 };
  47
  48 static struct irqaction irq_cascade3 = {
  49         .handler = no_action,
  50         .name = "RTL838X IRQ cascade3",
  51 };
  52
  53 static struct irqaction irq_cascade4 = {
  54         .handler = no_action,
  55         .name = "RTL838X IRQ cascade4",
  56 };
  57
  58 static struct irqaction irq_cascade5 = {
  59         .handler = no_action,
  60         .name = "RTL838X IRQ cascade5",
  61 };
  62
  63 static void rtl838x_ictl_enable_irq(struct irq_data *i)
  64 {
  65         unsigned long flags;
  66
  67         raw_spin_lock_irqsave(&irq_lock, flags);
  68         icu_w32_mask(0, 1 << i->irq, GIMR);
  69         raw_spin_unlock_irqrestore(&irq_lock, flags);
  70 }
  71
  72 static unsigned int rtl838x_ictl_startup_irq(struct irq_data *i)
  73 {
  74         rtl838x_ictl_enable_irq(i);
  75         return 0;
  76 }
  77
  78 static void rtl838x_ictl_disable_irq(struct irq_data *i)
  79 {
  80         unsigned long flags;
  81
  82         raw_spin_lock_irqsave(&irq_lock, flags);
  83         icu_w32_mask(1 << i->irq, 0, GIMR);
  84         raw_spin_unlock_irqrestore(&irq_lock, flags);
  85 }
  86
  87 static void rtl838x_ictl_eoi_irq(struct irq_data *i)
  88 {
  89         unsigned long flags;
  90
  91         raw_spin_lock_irqsave(&irq_lock, flags);
  92         icu_w32_mask(0, 1 << i->irq, GIMR);
  93         raw_spin_unlock_irqrestore(&irq_lock, flags);
  94 }
  95
  96 static struct irq_chip rtl838x_ictl_irq = {
  97         .name = "RTL838X",
  98         .irq_startup = rtl838x_ictl_startup_irq,
  99         .irq_shutdown = rtl838x_ictl_disable_irq,
 100         .irq_enable = rtl838x_ictl_enable_irq,
 101         .irq_disable = rtl838x_ictl_disable_irq,
 102         .irq_ack = rtl838x_ictl_disable_irq,
 103         .irq_mask = rtl838x_ictl_disable_irq,
 104         .irq_unmask = rtl838x_ictl_enable_irq,
 105         .irq_eoi = rtl838x_ictl_eoi_irq,
 106 };
 107
 108 /*
 109  *   RTL8390/80/28 Interrupt Scheme
 110  *
 111  *   Source       IRQ      CPU INT
 112  *   --------   -------    -------
 113  *   UART0          31        IP3
 114  *   UART1          30        IP2
 115  *   TIMER0         29        IP6
 116  *   TIMER1         28        IP2
 117  *   OCPTO          27        IP2
 118  *   HLXTO          26        IP2
 119  *   SLXTO          25        IP2
 120  *   NIC            24        IP5
 121  *   GPIO_ABCD      23        IP5
 122  *   SWCORE         20        IP4
 123  */
 124
 125 unsigned int rtl838x_ictl_irq_dispatch1(void)
 126 {
 127         /* Identify shared IRQ  */
 128         unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR);
 129
 130         if (extint_ip & TC1_IP)
 131                 do_IRQ(TC1_IRQ);
 132         else if (extint_ip & UART1_IP)
 133                 do_IRQ(UART1_IRQ);
 134         else
 135                 spurious_interrupt();
 136
 137         return IRQ_HANDLED;
 138 }
 139
 140 unsigned int rtl838x_ictl_irq_dispatch2(void)
 141 {
 142         do_IRQ(UART0_IRQ);
 143         return IRQ_HANDLED;
 144 }
 145
 146 unsigned int rtl838x_ictl_irq_dispatch3(void)
 147 {
 148         do_IRQ(SWCORE_IRQ);
 149         return IRQ_HANDLED;
 150 }
 151
 152 unsigned int rtl838x_ictl_irq_dispatch4(void)
 153 {
 154         /* Identify shared IRQ */
 155         unsigned int extint_ip = icu_r32(GIMR) & icu_r32(GISR);
 156
 157         if (extint_ip & NIC_IP)
 158                 do_IRQ(NIC_IRQ);
 159         else if (extint_ip & GPIO_ABCD_IP)
 160                 do_IRQ(GPIO_ABCD_IRQ);
 161         else if ((extint_ip & GPIO_EFGH_IP) && (soc_info.family == RTL8328_FAMILY_ID))
 162                 do_IRQ(GPIO_EFGH_IRQ);
 163         else
 164                 spurious_interrupt();
 165
 166         return IRQ_HANDLED;
 167 }
 168
 169 unsigned int rtl838x_ictl_irq_dispatch5(void)
 170 {
 171         do_IRQ(TC0_IRQ);
 172         return IRQ_HANDLED;
 173 }
 174
 175 asmlinkage void plat_irq_dispatch(void)
 176 {
 177         unsigned int pending;
 178
 179         pending =  read_c0_cause() & read_c0_status() & ST0_IM;
 180
 181         if (pending & CAUSEF_IP7)
 182                 c0_compare_interrupt(7, NULL);
 183         else if (pending & CAUSEF_IP6)
 184                 rtl838x_ictl_irq_dispatch5();
 185         else if (pending & CAUSEF_IP5)
 186                 rtl838x_ictl_irq_dispatch4();
 187         else if (pending & CAUSEF_IP4)
 188                 rtl838x_ictl_irq_dispatch3();
 189         else if (pending & CAUSEF_IP3)
 190                 rtl838x_ictl_irq_dispatch2();
 191         else if (pending & CAUSEF_IP2)
 192                 rtl838x_ictl_irq_dispatch1();
 193         else
 194                 spurious_interrupt();
 195 }
 196
 197 static void __init rtl838x_ictl_irq_init(unsigned int irq_base)
 198 {
 199         int i;
 200
 201         for (i = 0; i < RTL838X_IRQ_ICTL_NUM; i++)
 202                 irq_set_chip_and_handler(irq_base + i, &rtl838x_ictl_irq, handle_level_irq);
 203
 204         setup_irq(RTL838X_ICTL1_IRQ, &irq_cascade1);
 205         setup_irq(RTL838X_ICTL2_IRQ, &irq_cascade2);
 206         setup_irq(RTL838X_ICTL3_IRQ, &irq_cascade3);
 207         setup_irq(RTL838X_ICTL4_IRQ, &irq_cascade4);
 208         setup_irq(RTL838X_ICTL5_IRQ, &irq_cascade5);
 209
 210         /* Set GIMR, IRR */
 211         icu_w32(TC0_IE | UART0_IE, GIMR);
 212         icu_w32(IRR0_SETTING, IRR0);
 213         icu_w32(IRR1_SETTING, IRR1);
 214         icu_w32(IRR2_SETTING, IRR2);
 215         icu_w32(IRR3_SETTING, IRR3);
 216 }
 217
 218 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 219 {
 220         irq_set_chip_and_handler(hw, &rtl838x_ictl_irq, handle_level_irq);
 221
 222         return 0;
 223 }
 224
 225 static const struct irq_domain_ops irq_domain_ops = {
 226         .xlate = irq_domain_xlate_onecell,
 227         .map = intc_map,
 228 };
 229
 230 int __init icu_of_init(struct device_node *node, struct device_node *parent)
 231 {
 232         int i;
 233         struct irq_domain *domain;
 234         struct resource res;
 235
 236         pr_info("Found Interrupt controller: %s (%s)\n", node->name, node->full_name);
 237         if (of_address_to_resource(node, 0, &res)) {
 238                 panic("Failed to get icu memory range");
 239         }
 240         if (!request_mem_region(res.start, resource_size(&res), res.name))
 241                 pr_err("Failed to request icu memory\n");
 242         soc_info.icu_base = ioremap(res.start, resource_size(&res));
 243         pr_info("ICU Memory: %08x\n", (u32)soc_info.icu_base);
 244
 245         mips_cpu_irq_init();
 246
 247         domain = irq_domain_add_simple(node, 32, 0, &irq_domain_ops, NULL);
 248
 249         /* Setup all external HW irqs */
 250         for (i = 8; i < 32; i++)
 251                 irq_domain_associate(domain, i, i);
 252
 253         rtl838x_ictl_irq_init(RTL838X_IRQ_ICTL_BASE);
 254         return 0;
 255 }
 256
 257 void __init arch_init_irq(void)
 258 {
 259         /* do board-specific irq initialization */
 260         irqchip_init();
 261 }
 262
 263 IRQCHIP_DECLARE(mips_cpu_intc, "rtl838x,icu", icu_of_init);