1 // SPDX-License-Identifier: GPL-2.0-only
3 * Realtek RTL838X architecture specific IRQ handling
5 * Copyright (C) 2020 B. Koblitz
6 * based on the original BSP
7 * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_address.h>
17 #include <linux/spinlock.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
21 #include <mach-rtl838x.h>
23 #define icu_r32(reg) rtl838x_r32(soc_info.icu_base + reg)
24 #define icu_w32(val, reg) rtl838x_w32(val, soc_info.icu_base + reg)
25 #define icu_w32_mask(clear, set, reg) rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
27 static DEFINE_RAW_SPINLOCK(irq_lock
);
29 extern irqreturn_t
c0_compare_interrupt(int irq
, void *dev_id
);
32 static void rtl838x_ictl_enable_irq(struct irq_data
*i
)
36 raw_spin_lock_irqsave(&irq_lock
, flags
);
37 icu_w32_mask(0, 1 << i
->irq
, GIMR
);
38 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
41 static void rtl838x_ictl_disable_irq(struct irq_data
*i
)
45 raw_spin_lock_irqsave(&irq_lock
, flags
);
46 icu_w32_mask(1 << i
->irq
, 0, GIMR
);
47 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
50 static void rtl838x_ictl_eoi_irq(struct irq_data
*i
)
54 raw_spin_lock_irqsave(&irq_lock
, flags
);
55 icu_w32_mask(0, 1 << i
->irq
, GIMR
);
56 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
59 static struct irq_chip rtl838x_ictl_irq
= {
61 .irq_enable
= rtl838x_ictl_enable_irq
,
62 .irq_disable
= rtl838x_ictl_disable_irq
,
63 .irq_ack
= rtl838x_ictl_disable_irq
,
64 .irq_mask
= rtl838x_ictl_disable_irq
,
65 .irq_unmask
= rtl838x_ictl_enable_irq
,
66 .irq_eoi
= rtl838x_ictl_eoi_irq
,
70 * RTL8390/80/28 Interrupt Scheme
73 * -------- ------- -------
86 asmlinkage
void plat_irq_dispatch(void)
88 unsigned int pending
, ext_int
;
90 pending
= read_c0_cause();
92 if (pending
& CAUSEF_IP7
) {
93 c0_compare_interrupt(7, NULL
);
94 } else if (pending
& CAUSEF_IP6
) {
96 } else if (pending
& CAUSEF_IP5
) {
97 ext_int
= icu_r32(GIMR
) & icu_r32(GISR
);
100 else if (ext_int
& GPIO_ABCD_IP
)
101 do_IRQ(GPIO_ABCD_IRQ
);
102 else if ((ext_int
& GPIO_EFGH_IP
) && (soc_info
.family
== RTL8328_FAMILY_ID
))
103 do_IRQ(GPIO_EFGH_IRQ
);
105 spurious_interrupt();
106 } else if (pending
& CAUSEF_IP4
) {
108 } else if (pending
& CAUSEF_IP3
) {
110 } else if (pending
& CAUSEF_IP2
) {
111 ext_int
= icu_r32(GIMR
) & icu_r32(GISR
);
112 if (ext_int
& TC1_IP
)
114 else if (ext_int
& UART1_IP
)
117 spurious_interrupt();
119 spurious_interrupt();
123 static int intc_map(struct irq_domain
*d
, unsigned int irq
, irq_hw_number_t hw
)
125 irq_set_chip_and_handler(hw
, &rtl838x_ictl_irq
, handle_level_irq
);
130 static const struct irq_domain_ops irq_domain_ops
= {
131 .xlate
= irq_domain_xlate_onecell
,
135 int __init
icu_of_init(struct device_node
*node
, struct device_node
*parent
)
138 struct irq_domain
*domain
;
141 pr_info("Found Interrupt controller: %s (%s)\n", node
->name
, node
->full_name
);
142 if (of_address_to_resource(node
, 0, &res
))
143 panic("Failed to get icu memory range");
145 if (!request_mem_region(res
.start
, resource_size(&res
), res
.name
))
146 pr_err("Failed to request icu memory\n");
148 soc_info
.icu_base
= ioremap(res
.start
, resource_size(&res
));
149 pr_info("ICU Memory: %08x\n", (u32
)soc_info
.icu_base
);
153 domain
= irq_domain_add_simple(node
, 32, 0, &irq_domain_ops
, NULL
);
155 /* Setup all external HW irqs */
156 for (i
= 8; i
< RTL838X_IRQ_ICTL_NUM
; i
++) {
157 irq_domain_associate(domain
, i
, i
);
158 irq_set_chip_and_handler(RTL838X_IRQ_ICTL_BASE
+ i
,
159 &rtl838x_ictl_irq
, handle_level_irq
);
162 if (request_irq(RTL838X_ICTL1_IRQ
, no_action
, IRQF_NO_THREAD
,
163 "IRQ cascade 1", NULL
)) {
164 pr_err("request_irq() cascade 1 for irq %d failed\n", RTL838X_ICTL1_IRQ
);
166 if (request_irq(RTL838X_ICTL2_IRQ
, no_action
, IRQF_NO_THREAD
,
167 "IRQ cascade 2", NULL
)) {
168 pr_err("request_irq() cascade 2 for irq %d failed\n", RTL838X_ICTL2_IRQ
);
170 if (request_irq(RTL838X_ICTL3_IRQ
, no_action
, IRQF_NO_THREAD
,
171 "IRQ cascade 3", NULL
)) {
172 pr_err("request_irq() cascade 3 for irq %d failed\n", RTL838X_ICTL3_IRQ
);
174 if (request_irq(RTL838X_ICTL4_IRQ
, no_action
, IRQF_NO_THREAD
,
175 "IRQ cascade 4", NULL
)) {
176 pr_err("request_irq() cascade 4 for irq %d failed\n", RTL838X_ICTL4_IRQ
);
178 if (request_irq(RTL838X_ICTL5_IRQ
, no_action
, IRQF_NO_THREAD
,
179 "IRQ cascade 5", NULL
)) {
180 pr_err("request_irq() cascade 5 for irq %d failed\n", RTL838X_ICTL5_IRQ
);
183 /* Set up interrupt routing scheme */
184 icu_w32(IRR0_SETTING
, IRR0
);
185 if (soc_info
.family
== RTL8380_FAMILY_ID
)
186 icu_w32(IRR1_SETTING_RTL838X
, IRR1
);
188 icu_w32(IRR1_SETTING_RTL839X
, IRR1
);
189 icu_w32(IRR2_SETTING
, IRR2
);
190 icu_w32(IRR3_SETTING
, IRR3
);
192 /* Enable timer0 and uart0 interrupts */
193 icu_w32(TC0_IE
| UART0_IE
, GIMR
);
197 void __init
arch_init_irq(void)
199 /* do board-specific irq initialization */
203 IRQCHIP_DECLARE(mips_cpu_intc
, "rtl838x,icu", icu_of_init
);