target/linux/rtl838x/files-5.4/arch/mips/rtl838x/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Setup for the Realtek RTL838X SoC:
   4  *      Memory, Timer and Serial
   5  *
   6  * Copyright (C) 2020 B. Koblitz
   7  * based on the original BSP by
   8  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   9  *
  10  */
  11 #include <linux/console.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/clk-provider.h>
  16
  17 #include <asm/addrspace.h>
  18 #include <asm/io.h>
  19
  20 #include <asm/bootinfo.h>
  21 #include <linux/of_fdt.h>
  22 #include <asm/reboot.h>
  23 #include <asm/time.h>           /* for mips_hpt_frequency */
  24 #include <asm/prom.h>
  25 #include <asm/smp-ops.h>
  26
  27 #include "mach-rtl838x.h"
  28
  29 extern int rtl838x_serial_init(void);
  30 extern struct rtl838x_soc_info soc_info;
  31
  32 struct clk {
  33         struct clk_lookup cl;
  34         unsigned long rate;
  35 };
  36
  37 struct clk cpu_clk;
  38
  39 u32 pll_reset_value;
  40
  41 static void rtl838x_restart(char *command)
  42 {
  43         u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
  44          /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
  45         void (*f)(void) = (void *) 0xbfc00000;
  46
  47         pr_info("System restart.\n");
  48         if (soc_info.family == RTL8390_FAMILY_ID) {
  49                 f();
  50                 /* If calling reset vector fails, reset entire chip */
  51                 sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
  52                 /* If this fails, halt the CPU */
  53                 while
  54                         (1);
  55         }
  56
  57         pr_info("PLL control register: %x, applying reset value %x\n",
  58                 pll, pll_reset_value);
  59         sw_w32(3, RTL838X_INT_RW_CTRL);
  60         sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
  61         sw_w32(0, RTL838X_INT_RW_CTRL);
  62
  63         pr_info("Resetting RTL838X SoC\n");
  64         /* Reset Global Control1 Register */
  65         sw_w32(1, RTL838X_RST_GLB_CTRL_1);
  66 }
  67
  68 static void rtl838x_halt(void)
  69 {
  70         pr_info("System halted.\n");
  71         while
  72                 (1);
  73 }
  74
  75 static void __init rtl838x_setup(void)
  76 {
  77         unsigned int val;
  78
  79         pr_info("Registering _machine_restart\n");
  80         _machine_restart = rtl838x_restart;
  81         _machine_halt = rtl838x_halt;
  82
  83         val = rtl838x_r32((volatile void *)0xBB0040000);
  84         if (val == 3)
  85                 pr_info("PCI device found\n");
  86         else
  87                 pr_info("NO PCI device found\n");
  88
  89         /* Setup System LED. Bit 15 (14 for RTL8390) then allows to toggle it */
  90         if (soc_info.family == RTL8380_FAMILY_ID)
  91                 sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
  92         else
  93                 sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
  94 }
  95
  96 void __init plat_mem_setup(void)
  97 {
  98         void *dtb;
  99
 100         pr_info("%s called\n", __func__);
 101
 102         set_io_port_base(KSEG1);
 103
 104         if (fw_passed_dtb) /* UHI interface */
 105                 dtb = (void *)fw_passed_dtb;
 106         else if (__dtb_start != __dtb_end)
 107                 dtb = (void *)__dtb_start;
 108         else
 109                 panic("no dtb found");
 110
 111         /*
 112          * Load the devicetree. This causes the chosen node to be
 113          * parsed resulting in our memory appearing
 114          */
 115         __dt_setup_arch(dtb);
 116
 117         rtl838x_setup();
 118 }
 119
 120
 121 /*
 122  * Linux clock API
 123  */
 124 int clk_enable(struct clk *clk)
 125 {
 126         return 0;
 127 }
 128 EXPORT_SYMBOL_GPL(clk_enable);
 129
 130 void clk_disable(struct clk *clk)
 131 {
 132
 133 }
 134 EXPORT_SYMBOL_GPL(clk_disable);
 135
 136 unsigned long clk_get_rate(struct clk *clk)
 137 {
 138         if (!clk)
 139                 return 0;
 140
 141         return clk->rate;
 142 }
 143 EXPORT_SYMBOL_GPL(clk_get_rate);
 144
 145 int clk_set_rate(struct clk *clk, unsigned long rate)
 146 {
 147         return -1;
 148 }
 149 EXPORT_SYMBOL_GPL(clk_set_rate);
 150
 151 long clk_round_rate(struct clk *clk, unsigned long rate)
 152 {
 153         return -1;
 154 }
 155 EXPORT_SYMBOL_GPL(clk_round_rate);
 156
 157 void __init plat_time_init(void)
 158 {
 159         u32 freq = 500000000;
 160         struct device_node *np;
 161         struct clk *clk = &cpu_clk;
 162
 163         np = of_find_node_by_name(NULL, "cpus");
 164         if (!np) {
 165                 pr_err("Missing 'cpus' DT node, using default frequency.");
 166         } else {
 167                 if (of_property_read_u32(np, "frequency", &freq) < 0)
 168                         pr_err("No 'frequency' property in DT, using default.");
 169                 else
 170                         pr_info("CPU frequency from device tree: %d", freq);
 171                 of_node_put(np);
 172         }
 173
 174         clk->rate = freq;
 175
 176         if (IS_ERR(clk))
 177                 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 178
 179         pr_info("CPU Clock: %ld MHz\n", clk->rate / 1000000);
 180         mips_hpt_frequency = freq / 2;
 181
 182         pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
 183         pr_info("PLL control register: %x\n", pll_reset_value);
 184
 185         /* With the info from the command line and cpu-freq we can setup the console */
 186         rtl838x_serial_init();
 187 }