1 // SPDX-License-Identifier: GPL-2.0-only
3 * Setup for the Realtek RTL838X SoC:
4 * Memory, Timer and Serial
6 * Copyright (C) 2020 B. Koblitz
7 * based on the original BSP by
8 * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
12 #include <linux/console.h>
13 #include <linux/init.h>
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/clk-provider.h>
18 #include <asm/addrspace.h>
21 #include <asm/bootinfo.h>
22 #include <linux/of_fdt.h>
23 #include <asm/reboot.h>
24 #include <asm/time.h> /* for mips_hpt_frequency */
26 #include <asm/smp-ops.h>
28 #include "mach-rtl838x.h"
30 extern int rtl838x_serial_init(void);
31 struct rtl838x_soc_info soc_info
;
42 static void rtl838x_restart(char *command
)
44 u32 pll
= sw_r32(RTL838X_PLL_CML_CTRL
);
45 /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
46 void (*f
)(void) = (void *) 0xbfc00000;
48 pr_info("System restart.\n");
49 if (soc_info
.family
== RTL8390_FAMILY_ID
) {
51 /* If calling reset vector fails, reset entire chip */
52 sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL
);
53 /* If this fails, halt the CPU */
58 pr_info("PLL control register: %x, applying reset value %x\n",
59 pll
, pll_reset_value
);
60 sw_w32(3, RTL838X_INT_RW_CTRL
);
61 sw_w32(pll_reset_value
, RTL838X_PLL_CML_CTRL
);
62 sw_w32(0, RTL838X_INT_RW_CTRL
);
64 pr_info("Resetting RTL838X SoC\n");
65 /* Reset Global Control1 Register */
66 sw_w32(1, RTL838X_RST_GLB_CTRL_1
);
69 static void rtl838x_halt(void)
71 pr_info("System halted.\n");
76 static void __init
rtl838x_setup(void)
80 pr_info("Registering _machine_restart\n");
81 _machine_restart
= rtl838x_restart
;
82 _machine_halt
= rtl838x_halt
;
84 val
= rtl838x_r32((volatile void *)0xBB0040000);
86 pr_info("PCI device found\n");
88 pr_info("NO PCI device found\n");
90 /* Setup System LED. Bit 15 (14 for RTL8390) then allows to toggle it */
91 if (soc_info
.family
== RTL8380_FAMILY_ID
)
92 sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL
);
94 sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL
);
97 void __init
plat_mem_setup(void)
101 pr_info("%s called\n", __func__
);
103 set_io_port_base(KSEG1
);
105 if (fw_passed_dtb
) /* UHI interface */
106 dtb
= (void *)fw_passed_dtb
;
107 else if (__dtb_start
!= __dtb_end
)
108 dtb
= (void *)__dtb_start
;
110 panic("no dtb found");
113 * Load the devicetree. This causes the chosen node to be
114 * parsed resulting in our memory appearing
116 __dt_setup_arch(dtb
);
125 int clk_enable(struct clk
*clk
)
129 EXPORT_SYMBOL_GPL(clk_enable
);
131 void clk_disable(struct clk
*clk
)
135 EXPORT_SYMBOL_GPL(clk_disable
);
137 unsigned long clk_get_rate(struct clk
*clk
)
144 EXPORT_SYMBOL_GPL(clk_get_rate
);
146 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
150 EXPORT_SYMBOL_GPL(clk_set_rate
);
152 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
156 EXPORT_SYMBOL_GPL(clk_round_rate
);
158 void __init
plat_time_init(void)
160 u32 freq
= 500000000;
161 struct device_node
*np
;
162 struct clk
*clk
= &cpu_clk
;
164 np
= of_find_node_by_name(NULL
, "cpus");
166 pr_err("Missing 'cpus' DT node, using default frequency.");
168 if (of_property_read_u32(np
, "frequency", &freq
) < 0)
169 pr_err("No 'frequency' property in DT, using default.");
171 pr_info("CPU frequency from device tree: %d", freq
);
178 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk
));
180 pr_info("CPU Clock: %ld MHz\n", clk
->rate
/ 1000000);
181 mips_hpt_frequency
= freq
/ 2;
183 pll_reset_value
= sw_r32(RTL838X_PLL_CML_CTRL
);
184 pr_info("PLL control register: %x\n", pll_reset_value
);
186 /* With the info from the command line and cpu-freq we can setup the console */
187 rtl838x_serial_init();