1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/device.h>
4 #include <linux/init.h>
5 #include <linux/module.h>
6 #include <linux/mutex.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/spi-nor.h>
15 #include "rtl838x-spi.h"
16 #include <asm/mach-rtl838x/mach-rtl838x.h>
18 extern struct rtl838x_soc_info soc_info
;
23 volatile void __iomem
*base
;
30 static uint32_t spi_prep(struct rtl838x_nor
*rtl838x_nor
)
32 /* Needed because of MMU constraints */
34 spi_w32w(SPI_CS_INIT
, SFCSR
); //deactivate CS0, CS1
35 spi_w32w(0, SFCSR
); //activate CS0,CS1
36 spi_w32w(SPI_CS_INIT
, SFCSR
); //deactivate CS0, CS1
38 return (CS0
& rtl838x_nor
->flags
) ? (SPI_eCS0
& SPI_LEN_INIT
)
39 : ((SPI_eCS1
& SPI_LEN_INIT
) | SFCSR_CHIP_SEL
);
42 static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor
*rtl838x_nor
)
46 sfcsr
= spi_prep(rtl838x_nor
);
47 sfdr
= (SPINOR_OP_RDSR
)<<24;
49 pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__
, sfcsr
, sfdr
);
50 pr_debug("rdid,sfcsr = %.8x\n", sfcsr
| SPI_LEN4
);
51 spi_w32w(sfcsr
, SFCSR
);
53 spi_w32_mask(0, SPI_LEN4
, SFCSR
);
59 static void spi_write_disable(struct rtl838x_nor
*rtl838x_nor
)
63 sfcsr
= spi_prep(rtl838x_nor
);
64 sfdr
= (SPINOR_OP_WRDI
) << 24;
65 spi_w32w(sfcsr
, SFCSR
);
67 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__
, sfcsr
, sfdr
);
69 spi_prep(rtl838x_nor
);
72 static void spi_write_enable(struct rtl838x_nor
*rtl838x_nor
)
76 sfcsr
= spi_prep(rtl838x_nor
);
77 sfdr
= (SPINOR_OP_WREN
) << 24;
78 spi_w32w(sfcsr
, SFCSR
);
80 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__
, sfcsr
, sfdr
);
82 spi_prep(rtl838x_nor
);
85 static void spi_4b_set(struct rtl838x_nor
*rtl838x_nor
, bool enable
)
89 sfcsr
= spi_prep(rtl838x_nor
);
91 sfdr
= (SPINOR_OP_EN4B
) << 24;
93 sfdr
= (SPINOR_OP_EX4B
) << 24;
95 spi_w32w(sfcsr
, SFCSR
);
97 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__
, sfcsr
, sfdr
);
99 spi_prep(rtl838x_nor
);
102 static int rtl838x_get_addr_mode(struct rtl838x_nor
*rtl838x_nor
)
107 sw_w32(0x3, RTL838X_INT_RW_CTRL
);
108 if (!sw_r32(RTL838X_EXT_VERSION
)) {
109 if (sw_r32(RTL838X_STRAP_DBG
) & (1 << 29))
112 reg
= sw_r32(RTL838X_PLL_CML_CTRL
);
113 if ((reg
& (1 << 30)) && (reg
& (1 << 31)))
115 if ((!(reg
& (1 << 30)))
116 && sw_r32(RTL838X_STRAP_DBG
) & (1 << 29))
119 sw_w32(0x0, RTL838X_INT_RW_CTRL
);
123 static int rtl8390_get_addr_mode(struct rtl838x_nor
*rtl838x_nor
)
125 if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF
) & (1 << 9))
130 ssize_t
rtl838x_do_read(struct rtl838x_nor
*rtl838x_nor
, loff_t from
,
131 size_t length
, u_char
*buffer
, uint8_t command
)
133 uint32_t sfcsr
, sfdr
;
134 uint32_t len
= length
;
136 sfcsr
= spi_prep(rtl838x_nor
);
137 sfdr
= command
<< 24;
139 /* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
143 spi_w32w(sfcsr
, SFCSR
);
144 spi_w32w(sfdr
, SFDR
);
146 /* Read Data, 4 bytes at a time */
147 while (length
>= 4) {
149 *((uint32_t *) buffer
) = spi_r32(SFDR
);
154 /* The rest needs to be read 1 byte a time */
155 sfcsr
&= SPI_LEN_INIT
|SPI_LEN1
;
157 spi_w32w(sfcsr
, SFCSR
);
160 *(buffer
) = spi_r32(SFDR
) >> 24;
168 * Do fast read in 3 or 4 Byte addressing mode
170 static ssize_t
rtl838x_do_4bf_read(struct rtl838x_nor
*rtl838x_nor
, loff_t from
,
171 size_t length
, u_char
*buffer
, uint8_t command
)
173 int sfcsr_addr_len
= rtl838x_nor
->fourByteMode
? 0x3 : 0x2;
174 int sfdr_addr_shift
= rtl838x_nor
->fourByteMode
? 0 : 8;
176 uint32_t len
= length
;
178 pr_debug("Fast read from %llx, len %x, shift %d\n",
179 from
, sfcsr_addr_len
, sfdr_addr_shift
);
180 sfcsr
= spi_prep(rtl838x_nor
);
182 /* Send read command */
183 spi_w32w(sfcsr
| SPI_LEN1
, SFCSR
);
184 spi_w32w(command
<< 24, SFDR
);
187 spi_w32w(sfcsr
| (sfcsr_addr_len
<< 28), SFCSR
);
188 spi_w32w(from
<< sfdr_addr_shift
, SFDR
);
191 spi_w32w(sfcsr
| SPI_LEN1
, SFCSR
);
195 spi_w32w(sfcsr
| SPI_LEN4
, SFCSR
);
197 /* Read Data, 4 bytes at a time */
198 while (length
>= 4) {
200 *((uint32_t *) buffer
) = spi_r32(SFDR
);
205 /* The rest needs to be read 1 byte a time */
206 sfcsr
&= SPI_LEN_INIT
|SPI_LEN1
;
208 spi_w32w(sfcsr
, SFCSR
);
211 *(buffer
) = spi_r32(SFDR
) >> 24;
220 * Do write (Page Programming) in 3 or 4 Byte addressing mode
222 static ssize_t
rtl838x_do_4b_write(struct rtl838x_nor
*rtl838x_nor
, loff_t to
,
223 size_t length
, const u_char
*buffer
,
226 int sfcsr_addr_len
= rtl838x_nor
->fourByteMode
? 0x3 : 0x2;
227 int sfdr_addr_shift
= rtl838x_nor
->fourByteMode
? 0 : 8;
229 uint32_t len
= length
;
231 pr_debug("Write to %llx, len %x, shift %d\n",
232 to
, sfcsr_addr_len
, sfdr_addr_shift
);
233 sfcsr
= spi_prep(rtl838x_nor
);
235 /* Send write command, command IO-width is 1 (bit 25/26) */
236 spi_w32w(sfcsr
| SPI_LEN1
| (0 << 25), SFCSR
);
237 spi_w32w(command
<< 24, SFDR
);
240 spi_w32w(sfcsr
| (sfcsr_addr_len
<< 28) | (0 << 25), SFCSR
);
241 spi_w32w(to
<< sfdr_addr_shift
, SFDR
);
243 /* Write Data, 1 byte at a time, if we are not 4-byte aligned */
244 if (((long)buffer
) % 4) {
245 spi_w32w(sfcsr
| SPI_LEN1
, SFCSR
);
246 while (length
> 0 && (((long)buffer
) % 4)) {
248 spi_w32(*(buffer
) << 24, SFDR
);
254 /* Now we can write 4 bytes at a time */
256 spi_w32w(sfcsr
| SPI_LEN4
, SFCSR
);
257 while (length
>= 4) {
259 spi_w32(*((uint32_t *)buffer
), SFDR
);
264 /* Final bytes might need to be written 1 byte at a time, again */
266 spi_w32w(sfcsr
| SPI_LEN1
, SFCSR
);
269 spi_w32(*(buffer
) << 24, SFDR
);
276 static ssize_t
rtl838x_nor_write(struct spi_nor
*nor
, loff_t to
, size_t len
,
277 const u_char
*buffer
)
281 struct rtl838x_nor
*rtl838x_nor
= nor
->priv
;
283 uint8_t cmd
= SPINOR_OP_PP
;
285 /* Do write in 4-byte mode on large Macronix chips */
286 if (rtl838x_nor
->fourByteMode
) {
287 cmd
= SPINOR_OP_PP_4B
;
288 spi_4b_set(rtl838x_nor
, true);
291 pr_debug("In %s %8x to: %llx\n", __func__
,
292 (unsigned int) rtl838x_nor
, to
);
294 while (l
>= SPI_MAX_TRANSFER_SIZE
) {
296 (rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WIP
);
298 spi_write_enable(rtl838x_nor
);
299 } while (!(rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WEL
));
300 ret
= rtl838x_do_4b_write(rtl838x_nor
, to
+ offset
,
301 SPI_MAX_TRANSFER_SIZE
, buffer
+offset
, cmd
);
302 l
-= SPI_MAX_TRANSFER_SIZE
;
303 offset
+= SPI_MAX_TRANSFER_SIZE
;
308 (rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WIP
);
310 spi_write_enable(rtl838x_nor
);
311 } while (!(rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WEL
));
312 ret
= rtl838x_do_4b_write(rtl838x_nor
, to
+offset
,
313 len
, buffer
+offset
, cmd
);
319 static ssize_t
rtl838x_nor_read(struct spi_nor
*nor
, loff_t from
,
320 size_t length
, u_char
*buffer
)
323 uint8_t cmd
= SPINOR_OP_READ_FAST
;
325 struct rtl838x_nor
*rtl838x_nor
= nor
->priv
;
327 /* Do fast read in 3, or 4-byte mode on large Macronix chips */
328 if (rtl838x_nor
->fourByteMode
) {
329 cmd
= SPINOR_OP_READ_FAST_4B
;
330 spi_4b_set(rtl838x_nor
, true);
333 /* TODO: do timeout and return error */
334 pr_debug("Waiting for pending writes\n");
336 (rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WIP
);
338 spi_write_enable(rtl838x_nor
);
339 } while (!(rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WEL
));
341 pr_debug("cmd is %d\n", cmd
);
342 pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__
,
343 from
, (u32
)buffer
, (u32
)cmd
, length
);
345 while (l
>= SPI_MAX_TRANSFER_SIZE
) {
346 rtl838x_do_4bf_read(rtl838x_nor
, from
+ offset
,
347 SPI_MAX_TRANSFER_SIZE
, buffer
+offset
, cmd
);
348 l
-= SPI_MAX_TRANSFER_SIZE
;
349 offset
+= SPI_MAX_TRANSFER_SIZE
;
353 rtl838x_do_4bf_read(rtl838x_nor
, from
+ offset
, l
, buffer
+offset
, cmd
);
358 static int rtl838x_erase(struct spi_nor
*nor
, loff_t offs
)
360 struct rtl838x_nor
*rtl838x_nor
= nor
->priv
;
361 int sfcsr_addr_len
= rtl838x_nor
->fourByteMode
? 0x3 : 0x2;
362 int sfdr_addr_shift
= rtl838x_nor
->fourByteMode
? 0 : 8;
364 uint8_t cmd
= SPINOR_OP_SE
;
366 pr_debug("Erasing sector at %llx\n", offs
);
368 /* Do erase in 4-byte mode on large Macronix chips */
369 if (rtl838x_nor
->fourByteMode
) {
370 cmd
= SPINOR_OP_SE_4B
;
371 spi_4b_set(rtl838x_nor
, true);
373 /* TODO: do timeout and return error */
375 (rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WIP
);
377 spi_write_enable(rtl838x_nor
);
378 } while (!(rtl838x_nor_get_SR(rtl838x_nor
) & SPI_WEL
));
380 sfcsr
= spi_prep(rtl838x_nor
);
382 /* Send erase command, command IO-width is 1 (bit 25/26) */
383 spi_w32w(sfcsr
| SPI_LEN1
| (0 << 25), SFCSR
);
384 spi_w32w(cmd
<< 24, SFDR
);
387 spi_w32w(sfcsr
| (sfcsr_addr_len
<< 28) | (0 << 25), SFCSR
);
388 spi_w32w(offs
<< sfdr_addr_shift
, SFDR
);
393 static int rtl838x_nor_read_reg(struct spi_nor
*nor
, u8 opcode
, u8
*buf
, int len
)
397 uint32_t sfcsr
, sfdr
;
398 struct rtl838x_nor
*rtl838x_nor
= nor
->priv
;
400 pr_debug("In %s: opcode %x, len %x\n", __func__
, opcode
, len
);
402 sfcsr
= spi_prep(rtl838x_nor
);
407 spi_w32w(sfcsr
, SFCSR
);
408 spi_w32w(sfdr
, SFDR
);
412 *(buffer
) = spi_r32(SFDR
) >> 24;
420 static int rtl838x_nor_write_reg(struct spi_nor
*nor
, u8 opcode
, u8
*buf
, int len
)
422 uint32_t sfcsr
, sfdr
;
423 struct rtl838x_nor
*rtl838x_nor
= nor
->priv
;
425 pr_debug("In %s, opcode %x, len %x\n", __func__
, opcode
, len
);
426 sfcsr
= spi_prep(rtl838x_nor
);
429 if (len
== 1) { /* SPINOR_OP_WRSR */
433 spi_w32w(sfcsr
, SFCSR
);
434 spi_w32w(sfdr
, SFDR
);
438 static int spi_enter_sio(struct spi_nor
*nor
)
440 uint32_t sfcsr
, sfcr2
, sfdr
;
441 uint32_t ret
= 0, reg
= 0, size_bits
;
442 struct rtl838x_nor
*rtl838x_nor
= nor
->priv
;
444 pr_debug("In %s\n", __func__
);
445 rtl838x_nor
->io_status
= 0;
446 sfdr
= SPI_C_RSTQIO
<< 24;
447 sfcsr
= spi_prep(rtl838x_nor
);
449 reg
= spi_r32(SFCR2
);
450 pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg
, SFCR2_GETSIZE(reg
),
451 (reg
& SFCR2_RDOPT
));
452 size_bits
= rtl838x_nor
->fourByteMode
? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
454 sfcr2
= SFCR2_HOLD_TILL_SFDR2
| size_bits
455 | (reg
& SFCR2_RDOPT
) | SFCR2_CMDIO(0)
456 | SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
457 | SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST
);
458 pr_debug("SFCR2: %x, size %x\n", reg
, SFCR2_GETSIZE(reg
));
461 spi_w32w(sfcr2
, SFCR2
);
462 spi_w32w(sfcsr
, SFCSR
);
463 spi_w32w(sfdr
, SFDR
);
465 spi_w32_mask(SFCR2_HOLD_TILL_SFDR2
, 0, SFCR2
);
466 rtl838x_nor
->io_status
&= ~IOSTATUS_CIO_MASK
;
467 rtl838x_nor
->io_status
|= CIO1
;
469 spi_prep(rtl838x_nor
);
474 int rtl838x_spi_nor_scan(struct spi_nor
*nor
, const char *name
)
476 static const struct spi_nor_hwcaps hwcaps
= {
477 .mask
= SNOR_HWCAPS_READ
| SNOR_HWCAPS_PP
478 | SNOR_HWCAPS_READ_FAST
481 struct rtl838x_nor
*rtl838x_nor
= nor
->priv
;
483 pr_debug("In %s\n", __func__
);
485 spi_w32_mask(0, SFCR_EnableWBO
, SFCR
);
486 spi_w32_mask(0, SFCR_EnableRBO
, SFCR
);
488 rtl838x_nor
->flags
= CS0
| R_MODE
;
490 spi_nor_scan(nor
, NULL
, &hwcaps
);
491 pr_debug("------------- Got size: %llx\n", nor
->mtd
.size
);
496 int rtl838x_nor_init(struct rtl838x_nor
*rtl838x_nor
,
497 struct device_node
*flash_node
)
502 pr_info("%s called\n", __func__
);
503 nor
= &rtl838x_nor
->nor
;
504 nor
->dev
= rtl838x_nor
->dev
;
505 nor
->priv
= rtl838x_nor
;
506 spi_nor_set_flash_node(nor
, flash_node
);
508 nor
->read_reg
= rtl838x_nor_read_reg
;
509 nor
->write_reg
= rtl838x_nor_write_reg
;
510 nor
->read
= rtl838x_nor_read
;
511 nor
->write
= rtl838x_nor_write
;
512 nor
->erase
= rtl838x_erase
;
513 nor
->mtd
.name
= "rtl838x_nor";
514 nor
->erase_opcode
= rtl838x_nor
->fourByteMode
? SPINOR_OP_SE_4B
516 /* initialized with NULL */
517 ret
= rtl838x_spi_nor_scan(nor
, NULL
);
522 spi_write_disable(rtl838x_nor
);
524 ret
= mtd_device_parse_register(&nor
->mtd
, NULL
, NULL
, NULL
, 0);
528 static int rtl838x_nor_drv_probe(struct platform_device
*pdev
)
530 struct device_node
*flash_np
;
531 struct resource
*res
;
533 struct rtl838x_nor
*rtl838x_nor
;
536 pr_info("Initializing rtl838x_nor_driver\n");
537 if (!pdev
->dev
.of_node
) {
538 dev_err(&pdev
->dev
, "No DT found\n");
542 rtl838x_nor
= devm_kzalloc(&pdev
->dev
, sizeof(*rtl838x_nor
), GFP_KERNEL
);
545 platform_set_drvdata(pdev
, rtl838x_nor
);
547 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
548 rtl838x_nor
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
549 if (IS_ERR((void *)rtl838x_nor
->base
))
550 return PTR_ERR((void *)rtl838x_nor
->base
);
552 pr_info("SPI resource base is %08x\n", (u32
)rtl838x_nor
->base
);
553 rtl838x_nor
->dev
= &pdev
->dev
;
555 /* only support one attached flash */
556 flash_np
= of_get_next_available_child(pdev
->dev
.of_node
, NULL
);
558 dev_err(&pdev
->dev
, "no SPI flash device to configure\n");
563 /* Get the 3/4 byte address mode as configure by bootloader */
564 if (soc_info
.family
== RTL8390_FAMILY_ID
)
565 addrMode
= rtl8390_get_addr_mode(rtl838x_nor
);
567 addrMode
= rtl838x_get_addr_mode(rtl838x_nor
);
568 pr_info("Address mode is %d bytes\n", addrMode
);
570 rtl838x_nor
->fourByteMode
= true;
572 ret
= rtl838x_nor_init(rtl838x_nor
, flash_np
);
578 static int rtl838x_nor_drv_remove(struct platform_device
*pdev
)
580 /* struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
584 static const struct of_device_id rtl838x_nor_of_ids
[] = {
585 { .compatible
= "realtek,rtl838x-nor"},
588 MODULE_DEVICE_TABLE(of
, rtl838x_nor_of_ids
);
590 static struct platform_driver rtl838x_nor_driver
= {
591 .probe
= rtl838x_nor_drv_probe
,
592 .remove
= rtl838x_nor_drv_remove
,
594 .name
= "rtl838x-nor",
596 .of_match_table
= rtl838x_nor_of_ids
,
600 module_platform_driver(rtl838x_nor_driver
);
602 MODULE_LICENSE("GPL v2");
603 MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");