target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-mci.c

   1 /*
   2  *  linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
   3  *
   4  *  Copyright (C) 2007 Openmoko, Inc,  Andy Green <andy@openmoko.com>
   5  *  Based on S3C MMC driver that was:
   6  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mmc/mmc.h>
  15 #include <linux/mmc/sd.h>
  16 #include <linux/mmc/host.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/irq.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/crc7.h>
  24 #include <linux/scatterlist.h>
  25 #include <linux/io.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/mfd/glamo.h>
  28
  29 #include "glamo-core.h"
  30 #include "glamo-regs.h"
  31
  32 #define DRIVER_NAME "glamo-mci"
  33
  34 struct glamo_mci_host {
  35         struct platform_device *pdev;
  36         struct glamo_mmc_platform_data *pdata;
  37         struct mmc_host        *mmc;
  38         struct resource        *mmio_mem;
  39         struct resource        *data_mem;
  40         void __iomem           *mmio_base;
  41         u16 __iomem            *data_base;
  42
  43         struct regulator *regulator;
  44         struct mmc_request *mrq;
  45
  46         unsigned int clk_rate;
  47
  48         unsigned short vdd;
  49         char           power_mode;
  50
  51         unsigned char request_counter;
  52
  53         struct timer_list disable_timer;
  54
  55         struct work_struct irq_work;
  56
  57         unsigned clk_enabled : 1;
  58 };
  59
  60 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request* mrq);
  61 static void glamo_mci_send_command(struct glamo_mci_host *host,
  62                                   struct mmc_command *cmd);
  63
  64 /*
  65  * Max SD clock rate
  66  *
  67  * held at /(3 + 1) due to concerns of 100R recommended series resistor
  68  * allows 16MHz @ 4-bit --> 8MBytes/sec raw
  69  *
  70  * you can override this on kernel commandline using
  71  *
  72  *   glamo_mci.sd_max_clk=10000000
  73  *
  74  * for example
  75  */
  76
  77 static int sd_max_clk = 50000000;
  78 module_param(sd_max_clk, int, 0644);
  79
  80 /*
  81  * Slow SD clock rate
  82  *
  83  * you can override this on kernel commandline using
  84  *
  85  *   glamo_mci.sd_slow_ratio=8
  86  *
  87  * for example
  88  *
  89  * platform callback is used to decide effective clock rate, if not
  90  * defined then max is used, if defined and returns nonzero, rate is
  91  * divided by this factor
  92  */
  93
  94 static int sd_slow_ratio = 8;
  95 module_param(sd_slow_ratio, int, 0644);
  96
  97 /*
  98  * Post-power SD clock rate
  99  *
 100  * you can override this on kernel commandline using
 101  *
 102  *   glamo_mci.sd_post_power_clock=1000000
 103  *
 104  * for example
 105  *
 106  * After changing power to card, clock is held at this rate until first bulk
 107  * transfer completes
 108  */
 109
 110 static int sd_post_power_clock = 1000000;
 111 module_param(sd_post_power_clock, int, 0644);
 112
 113
 114 static inline void glamo_reg_write(struct glamo_mci_host *glamo,
 115                                 u_int16_t reg, u_int16_t val)
 116 {
 117         writew(val, glamo->mmio_base + reg);
 118 }
 119
 120 static inline u_int16_t glamo_reg_read(struct glamo_mci_host *glamo,
 121                                    u_int16_t reg)
 122 {
 123         return readw(glamo->mmio_base + reg);
 124 }
 125
 126 static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
 127                                 u_int16_t reg, u_int16_t mask,
 128                                 u_int16_t val)
 129 {
 130         u_int16_t tmp;
 131
 132         val &= mask;
 133
 134         tmp = glamo_reg_read(glamo, reg);
 135         tmp &= ~mask;
 136         tmp |= val;
 137         glamo_reg_write(glamo, reg, tmp);
 138 }
 139
 140 static void glamo_mci_clock_disable(struct glamo_mci_host *host) {
 141         if (host->clk_enabled) {
 142 /*              glamo_engine_div_disable(host->pdata->core, GLAMO_ENGINE_MMC);*/
 143                 host->clk_enabled = 0;
 144         printk("clk disabled\n");
 145         }
 146 }
 147
 148 static void glamo_mci_clock_enable(struct glamo_mci_host *host) {
 149         del_timer_sync(&host->disable_timer);
 150
 151         if (!host->clk_enabled) {
 152                 glamo_engine_div_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 153                 host->clk_enabled = 1;
 154         printk("clk enabled\n");
 155         }
 156 }
 157
 158 static void glamo_mci_disable_timer(unsigned long data) {
 159         struct glamo_mci_host *host = (struct glamo_mci_host *)data;
 160         glamo_mci_clock_disable(host);
 161 }
 162
 163
 164 static void do_pio_read(struct glamo_mci_host *host, struct mmc_data *data)
 165 {
 166         struct scatterlist *sg;
 167         u16 __iomem *from_ptr = host->data_base;
 168         void *sg_pointer;
 169
 170         dev_dbg(&host->pdev->dev, "pio_read():\n");
 171         for (sg = data->sg; sg; sg = sg_next(sg)) {
 172                 sg_pointer = page_address(sg_page(sg)) + sg->offset;
 173
 174
 175                 memcpy(sg_pointer, from_ptr, sg->length);
 176                 from_ptr += sg->length >> 1;
 177
 178                 data->bytes_xfered += sg->length;
 179         }
 180
 181         dev_dbg(&host->pdev->dev, "pio_read(): "
 182                         "complete (no more data).\n");
 183 }
 184
 185 static void do_pio_write(struct glamo_mci_host *host, struct mmc_data *data)
 186 {
 187         struct scatterlist *sg;
 188         u16 __iomem *to_ptr = host->data_base;
 189         void *sg_pointer;
 190
 191         dev_dbg(&host->pdev->dev, "pio_write():\n");
 192         for (sg = data->sg; sg; sg = sg_next(sg)) {
 193                 sg_pointer = page_address(sg_page(sg)) + sg->offset;
 194
 195                 data->bytes_xfered += sg->length;
 196
 197                 memcpy(to_ptr, sg_pointer, sg->length);
 198                 to_ptr += sg->length >> 1;
 199         }
 200
 201         dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
 202 }
 203
 204 static int glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq)
 205 {
 206         int real_rate = 0;
 207
 208         if (freq) {
 209                 glamo_mci_clock_enable(host);
 210                 real_rate = glamo_engine_reclock(host->pdata->core, GLAMO_ENGINE_MMC, freq);
 211         } else {
 212                 glamo_mci_clock_disable(host);
 213         }
 214
 215         return real_rate;
 216 }
 217
 218 static void glamo_mci_request_done(struct glamo_mci_host *host, struct
 219 mmc_request *mrq) {
 220         mod_timer(&host->disable_timer, jiffies + HZ / 16);
 221
 222         mmc_request_done(host->mmc, mrq);
 223 }
 224
 225
 226 static void glamo_mci_irq_worker(struct work_struct *work)
 227 {
 228         struct glamo_mci_host *host = container_of(work, struct glamo_mci_host,
 229                                                                                                 irq_work);
 230         struct mmc_command *cmd;
 231         uint16_t status;
 232
 233         if (!host->mrq || !host->mrq->cmd)
 234                 return;
 235
 236         cmd = host->mrq->cmd;
 237
 238         status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 239         dev_dbg(&host->pdev->dev, "status = 0x%04x\n", status);
 240
 241         /* we ignore a data timeout report if we are also told the data came */
 242         if (status & GLAMO_STAT1_MMC_RB_DRDY)
 243                 status &= ~GLAMO_STAT1_MMC_DTOUT;
 244
 245         if (status & (GLAMO_STAT1_MMC_RTOUT |
 246                           GLAMO_STAT1_MMC_DTOUT))
 247                 cmd->error = -ETIMEDOUT;
 248         if (status & (GLAMO_STAT1_MMC_BWERR |
 249                           GLAMO_STAT1_MMC_BRERR))
 250                 cmd->error = -EILSEQ;
 251         if (cmd->error) {
 252                 dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
 253                 goto done;
 254         }
 255
 256         /* issue STOP if we have been given one to use */
 257         if (host->mrq->stop)
 258                 glamo_mci_send_command(host, host->mrq->stop);
 259
 260         if (cmd->data->flags & MMC_DATA_READ)
 261                 do_pio_read(host, cmd->data);
 262
 263 done:
 264         host->mrq = NULL;
 265         glamo_mci_request_done(host, cmd->mrq);
 266 }
 267
 268 static irqreturn_t glamo_mci_irq(int irq, void *devid)
 269 {
 270         struct glamo_mci_host *host = (struct glamo_mci_host*)devid;
 271
 272         schedule_work(&host->irq_work);
 273
 274         return IRQ_HANDLED;
 275 }
 276
 277 static void glamo_mci_send_command(struct glamo_mci_host *host,
 278                                   struct mmc_command *cmd)
 279 {
 280         u8 u8a[6];
 281         u16 fire = 0;
 282         unsigned int timeout = 1000000;
 283         u16 * reg_resp = (u16 *)(host->mmio_base + GLAMO_REG_MMC_CMD_RSP1);
 284         u16 status;
 285         int triggers_int = 1;
 286
 287         /* if we can't do it, reject as busy */
 288         if (!glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
 289                  GLAMO_STAT1_MMC_IDLE) {
 290                 cmd->error = -EBUSY;
 291                 return;
 292         }
 293
 294         /* create an array in wire order for CRC computation */
 295         u8a[0] = 0x40 | (cmd->opcode & 0x3f);
 296         u8a[1] = (u8)(cmd->arg >> 24);
 297         u8a[2] = (u8)(cmd->arg >> 16);
 298         u8a[3] = (u8)(cmd->arg >> 8);
 299         u8a[4] = (u8)cmd->arg;
 300         u8a[5] = (crc7(0, u8a, 5) << 1) | 0x01; /* crc7 on first 5 bytes of packet */
 301
 302         /* issue the wire-order array including CRC in register order */
 303         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
 304         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
 305         glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
 306
 307         /* command index toggle */
 308         fire |= (host->request_counter & 1) << 12;
 309
 310         /* set type of command */
 311         switch (mmc_cmd_type(cmd)) {
 312         case MMC_CMD_BC:
 313                 fire |= GLAMO_FIRE_MMC_CMDT_BNR;
 314                 break;
 315         case MMC_CMD_BCR:
 316                 fire |= GLAMO_FIRE_MMC_CMDT_BR;
 317                 break;
 318         case MMC_CMD_AC:
 319                 fire |= GLAMO_FIRE_MMC_CMDT_AND;
 320                 break;
 321         case MMC_CMD_ADTC:
 322                 fire |= GLAMO_FIRE_MMC_CMDT_AD;
 323                 break;
 324         }
 325         /*
 326          * if it expects a response, set the type expected
 327          *
 328          * R1, Length  : 48bit, Normal response
 329          * R1b, Length : 48bit, same R1, but added card busy status
 330          * R2, Length  : 136bit (really 128 bits with CRC snipped)
 331          * R3, Length  : 48bit (OCR register value)
 332          * R4, Length  : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
 333          * R5, Length  : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
 334          * R6, Length  : 48bit (RCA register)
 335          * R7, Length  : 48bit (interface condition, VHS(voltage supplied),
 336          *                     check pattern, CRC7)
 337          */
 338         switch (mmc_resp_type(cmd)) {
 339         case MMC_RSP_R1: /* same index as R6 and R7 */
 340                 fire |= GLAMO_FIRE_MMC_RSPT_R1;
 341                 break;
 342         case MMC_RSP_R1B:
 343                 fire |= GLAMO_FIRE_MMC_RSPT_R1b;
 344                 break;
 345         case MMC_RSP_R2:
 346                 fire |= GLAMO_FIRE_MMC_RSPT_R2;
 347                 break;
 348         case MMC_RSP_R3:
 349                 fire |= GLAMO_FIRE_MMC_RSPT_R3;
 350                 break;
 351         /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
 352         }
 353         /*
 354          * From the command index, set up the command class in the host ctrllr
 355          *
 356          * missing guys present on chip but couldn't figure out how to use yet:
 357          *     0x0 "stream read"
 358          *     0x9 "cancel running command"
 359          */
 360         switch (cmd->opcode) {
 361         case MMC_READ_SINGLE_BLOCK:
 362                 fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
 363                 break;
 364         case MMC_SWITCH: /* 64 byte payload */
 365         case SD_APP_SEND_SCR:
 366         case MMC_READ_MULTIPLE_BLOCK:
 367                 /* we will get an interrupt off this */
 368                 if (!cmd->mrq->stop)
 369                         /* multiblock no stop */
 370                         fire |= GLAMO_FIRE_MMC_CC_MBRNS;
 371                 else
 372                          /* multiblock with stop */
 373                         fire |= GLAMO_FIRE_MMC_CC_MBRS;
 374                 break;
 375         case MMC_WRITE_BLOCK:
 376                 fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
 377                 break;
 378         case MMC_WRITE_MULTIPLE_BLOCK:
 379                 if (cmd->mrq->stop)
 380                          /* multiblock with stop */
 381                         fire |= GLAMO_FIRE_MMC_CC_MBWS;
 382                 else
 383                          /* multiblock NO stop-- 'RESERVED'? */
 384                         fire |= GLAMO_FIRE_MMC_CC_MBWNS;
 385                 break;
 386         case MMC_STOP_TRANSMISSION:
 387                 fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
 388                 triggers_int = 0;
 389                 break;
 390         default:
 391                 fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
 392                 triggers_int = 0;
 393                 break;
 394         }
 395
 396         if (triggers_int)
 397                 host->mrq = cmd->mrq;
 398
 399         /* always largest timeout */
 400         glamo_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
 401
 402         /* Generate interrupt on txfer */
 403         glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
 404                         0x0800 |
 405                         GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
 406                         GLAMO_BASIC_MMC_EN_COMPL_INT |
 407                         GLAMO_BASIC_MMC_EN_DATA_PUPS |
 408                         GLAMO_BASIC_MMC_EN_CMD_PUP);
 409
 410         /* send the command out on the wire */
 411         /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
 412         glamo_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
 413
 414         /* we are deselecting card?  because it isn't going to ack then... */
 415         if ((cmd->opcode == 7) && (cmd->arg == 0))
 416                 return;
 417
 418         /*
 419          * we must spin until response is ready or timed out
 420          * -- we don't get interrupts unless there is a bulk rx
 421          */
 422         do
 423                 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
 424         while (((((status >> 15) & 1) != (host->request_counter & 1)) ||
 425                 (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
 426                                  GLAMO_STAT1_MMC_RTOUT |
 427                                  GLAMO_STAT1_MMC_DTOUT |
 428                                  GLAMO_STAT1_MMC_BWERR |
 429                                  GLAMO_STAT1_MMC_BRERR)))) && (timeout--));
 430
 431         if ((status & (GLAMO_STAT1_MMC_RTOUT |
 432                                    GLAMO_STAT1_MMC_DTOUT)) ||
 433                 (timeout == 0)) {
 434                 cmd->error = -ETIMEDOUT;
 435         } else if (status & (GLAMO_STAT1_MMC_BWERR |
 436                           GLAMO_STAT1_MMC_BRERR)) {
 437                 cmd->error = -EILSEQ;
 438         }
 439
 440         if (cmd->flags & MMC_RSP_PRESENT) {
 441                 if (cmd->flags & MMC_RSP_136) {
 442                         cmd->resp[3] = readw(&reg_resp[0]) |
 443                                                    (readw(&reg_resp[1]) << 16);
 444                         cmd->resp[2] = readw(&reg_resp[2]) |
 445                                                    (readw(&reg_resp[3]) << 16);
 446                         cmd->resp[1] = readw(&reg_resp[4]) |
 447                                                    (readw(&reg_resp[5]) << 16);
 448                         cmd->resp[0] = readw(&reg_resp[6]) |
 449                                                    (readw(&reg_resp[7]) << 16);
 450                 } else {
 451                         cmd->resp[0] = (readw(&reg_resp[0]) >> 8) |
 452                                                    (readw(&reg_resp[1]) << 8) |
 453                                                    ((readw(&reg_resp[2])) << 24);
 454                 }
 455         }
 456 }
 457
 458 static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
 459                                  struct mmc_data *data)
 460 {
 461         /* set up the block info */
 462         glamo_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
 463         glamo_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
 464
 465         data->bytes_xfered = 0;
 466
 467         /* if write, prep the write into the shared RAM before the command */
 468         if (data->flags & MMC_DATA_WRITE) {
 469                 do_pio_write(host, data);
 470         }
 471
 472         dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
 473                                    data->blksz, data->blocks);
 474         return 0;
 475 }
 476
 477 static int glamo_mci_irq_poll(struct glamo_mci_host *host,
 478                                 struct mmc_command *cmd)
 479 {
 480         int timeout = 1000000;
 481         /*
 482          * if the glamo INT# line isn't wired (*cough* it can happen)
 483          * I'm afraid we have to spin on the IRQ status bit and "be
 484          * our own INT# line"
 485          */
 486         /*
 487          * we have faith we will get an "interrupt"...
 488          * but something insane like suspend problems can mean
 489          * we spin here forever, so we timeout after a LONG time
 490          */
 491         while ((!(readw(host->pdata->core->base +
 492                  GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
 493                    (timeout--));
 494
 495         if (timeout < 0) {
 496                 if (cmd->data->error)
 497                         cmd->data->error = -ETIMEDOUT;
 498                 dev_err(&host->pdev->dev, "Payload timeout\n");
 499                 return -ETIMEDOUT;
 500         }
 501         /* ack this interrupt source */
 502         writew(GLAMO_IRQ_MMC, host->pdata->core->base +
 503                    GLAMO_REG_IRQ_CLEAR);
 504
 505         /* yay we are an interrupt controller! -- call the ISR
 506          * it will stop clock to card
 507          */
 508         glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 509
 510         return 0;
 511 }
 512
 513 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request *mrq)
 514 {
 515         struct glamo_mci_host *host = mmc_priv(mmc);
 516         struct mmc_command *cmd = mrq->cmd;
 517
 518         host->request_counter++;
 519         if (cmd->data) {
 520                 if(glamo_mci_prepare_pio(host, cmd->data)) {
 521                         cmd->data->error = -EIO;
 522                         goto done;
 523                 }
 524         }
 525
 526         dev_dbg(&host->pdev->dev,"cmd 0x%x, "
 527                  "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
 528                  cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
 529                  cmd->flags);
 530
 531         glamo_mci_clock_enable(host);
 532         glamo_mci_send_command(host, cmd);
 533
 534         /*
 535          * if we don't have bulk data to take care of, we're done
 536          */
 537         if (!cmd->data || cmd->error)
 538                 goto done;
 539
 540
 541         if (!host->pdata->core->irq_works) {
 542                 if (glamo_mci_irq_poll(host, mrq->cmd))
 543                         goto done;
 544         }
 545
 546         /*
 547          * Otherwise can can use the interrupt as async completion --
 548          * if there is read data coming, or we wait for write data to complete,
 549          * exit without mmc_request_done() as the payload interrupt
 550          * will service it
 551          */
 552         dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
 553         return;
 554 done:
 555         glamo_mci_request_done(host, mrq);
 556 }
 557
 558 static void glamo_mci_set_power_mode(struct glamo_mci_host *host,
 559                                 unsigned char power_mode) {
 560         int ret;
 561
 562         if (power_mode == host->power_mode)
 563                 return;
 564
 565         switch(power_mode) {
 566         case MMC_POWER_UP:
 567                 if (host->power_mode == MMC_POWER_OFF) {
 568                         ret = regulator_enable(host->regulator);
 569                         if (ret)
 570                                 dev_err(&host->pdev->dev, "Failed to enable regulator: %d\n", ret);
 571                 }
 572                 break;
 573         case MMC_POWER_ON:
 574                 break;
 575         case MMC_POWER_OFF:
 576         default:
 577                 glamo_engine_disable(host->pdata->core,
 578                                      GLAMO_ENGINE_MMC);
 579
 580                 ret = regulator_disable(host->regulator);
 581                 if (ret)
 582                         dev_warn(&host->pdev->dev, "Failed to disable regulator: %d\n", ret);
 583                 break;
 584         }
 585         host->power_mode = power_mode;
 586 }
 587
 588 static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 589 {
 590         struct glamo_mci_host *host = mmc_priv(mmc);
 591         int bus_width = 0;
 592         int rate;
 593         int sd_drive;
 594         int ret;
 595
 596         /* Set power */
 597         glamo_mci_set_power_mode(host, ios->power_mode);
 598
 599         if (host->vdd != ios->vdd) {
 600                 ret = mmc_regulator_set_ocr(host->regulator, ios->vdd);
 601                 if (ret)
 602                         dev_err(&host->pdev->dev, "Failed to set regulator voltage: %d\n", ret);
 603                 else
 604                         host->vdd = ios->vdd;
 605         }
 606         rate = glamo_mci_set_card_clock(host, ios->clock);
 607
 608         if ((ios->power_mode == MMC_POWER_ON) ||
 609             (ios->power_mode == MMC_POWER_UP)) {
 610                 dev_info(&host->pdev->dev,
 611                         "powered (vdd = %hu) clk: %dkHz div=%hu (req: %ukHz). "
 612                         "Bus width=%d\n", ios->vdd,
 613                         rate / 1000, 0,
 614                         ios->clock / 1000, (int)ios->bus_width);
 615         } else {
 616                 dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
 617         }
 618
 619         /* set bus width */
 620         if (ios->bus_width == MMC_BUS_WIDTH_4)
 621                 bus_width = GLAMO_BASIC_MMC_EN_4BIT_DATA;
 622
 623         sd_drive = (rate * 4) / host->clk_rate;
 624         if (sd_drive > 3)
 625                 sd_drive = 3;
 626
 627         glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
 628                                                GLAMO_BASIC_MMC_EN_4BIT_DATA | 0xb0,
 629                                                    bus_width | sd_drive << 6);
 630 }
 631
 632
 633 /*
 634  * no physical write protect supported by us
 635  */
 636 static int glamo_mci_get_ro(struct mmc_host *mmc)
 637 {
 638         return 0;
 639 }
 640
 641 static struct mmc_host_ops glamo_mci_ops = {
 642         .request        = glamo_mci_send_request,
 643         .set_ios        = glamo_mci_set_ios,
 644         .get_ro         = glamo_mci_get_ro,
 645 };
 646
 647 static int glamo_mci_probe(struct platform_device *pdev)
 648 {
 649         struct mmc_host         *mmc;
 650         struct glamo_mci_host   *host;
 651         int ret;
 652
 653         dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
 654
 655         mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
 656         if (!mmc) {
 657                 ret = -ENOMEM;
 658                 goto probe_out;
 659         }
 660
 661         host = mmc_priv(mmc);
 662         host->mmc = mmc;
 663         host->pdev = pdev;
 664         host->pdata = pdev->dev.platform_data;
 665         host->power_mode = MMC_POWER_OFF;
 666         host->clk_enabled = 0;
 667
 668         INIT_WORK(&host->irq_work, glamo_mci_irq_worker);
 669
 670         host->regulator = regulator_get(pdev->dev.parent, "SD_3V3");
 671         if (!host->regulator) {
 672                 dev_err(&pdev->dev, "Cannot proceed without regulator.\n");
 673                 ret = -ENODEV;
 674                 goto probe_free_host;
 675         }
 676
 677         host->mmio_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 678         if (!host->mmio_mem) {
 679                 dev_err(&pdev->dev,
 680                         "failed to get io memory region resouce.\n");
 681                 ret = -ENOENT;
 682                 goto probe_regulator_put;
 683         }
 684
 685         host->mmio_mem = request_mem_region(host->mmio_mem->start,
 686                                             resource_size(host->mmio_mem),
 687                                             pdev->name);
 688
 689         if (!host->mmio_mem) {
 690                 dev_err(&pdev->dev, "failed to request io memory region.\n");
 691                 ret = -ENOENT;
 692                 goto probe_regulator_put;
 693         }
 694
 695         host->mmio_base = ioremap(host->mmio_mem->start,
 696                                   resource_size(host->mmio_mem));
 697         if (!host->mmio_base) {
 698                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
 699                 ret = -EINVAL;
 700                 goto probe_free_mem_region_mmio;
 701         }
 702
 703
 704         /* Get ahold of our data buffer we use for data in and out on MMC */
 705         host->data_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 706         if (!host->data_mem) {
 707                 dev_err(&pdev->dev,
 708                         "failed to get io memory region resource.\n");
 709                 ret = -ENOENT;
 710                 goto probe_iounmap_mmio;
 711         }
 712
 713         host->data_mem = request_mem_region(host->data_mem->start,
 714                                             resource_size(host->data_mem),
 715                                                                                 pdev->name);
 716
 717         if (!host->data_mem) {
 718                 dev_err(&pdev->dev, "failed to request io memory region.\n");
 719                 ret = -ENOENT;
 720                 goto probe_iounmap_mmio;
 721         }
 722         host->data_base = ioremap(host->data_mem->start,
 723                                   resource_size(host->data_mem));
 724
 725         if (host->data_base == 0) {
 726                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
 727                 ret = -EINVAL;
 728                 goto probe_free_mem_region_data;
 729         }
 730
 731         ret = request_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq, IRQF_SHARED,
 732                        pdev->name, host);
 733         if (ret) {
 734                 dev_err(&pdev->dev, "failed to register irq.\n");
 735                 goto probe_iounmap_data;
 736         }
 737
 738
 739         host->vdd = 0;
 740         host->clk_rate = glamo_pll_rate(host->pdata->core, GLAMO_PLL1);
 741
 742         /* explain our host controller capabilities */
 743         mmc->ops       = &glamo_mci_ops;
 744         mmc->ocr_avail = mmc_regulator_get_ocrmask(host->regulator);
 745         mmc->caps      = MMC_CAP_4_BIT_DATA |
 746                          MMC_CAP_MMC_HIGHSPEED |
 747                          MMC_CAP_SD_HIGHSPEED;
 748         mmc->f_min     = host->clk_rate / 256;
 749         mmc->f_max     = host->clk_rate;
 750
 751         mmc->max_blk_count = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
 752         mmc->max_blk_size  = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
 753         mmc->max_req_size  = resource_size(host->data_mem);
 754         mmc->max_seg_size  = mmc->max_req_size;
 755         mmc->max_phys_segs = 128;
 756         mmc->max_hw_segs   = 128;
 757
 758         if (mmc->ocr_avail < 0) {
 759                 dev_warn(&pdev->dev, "Failed to get ocr list for regulator: %d.\n",
 760                                 mmc->ocr_avail);
 761                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 762         }
 763
 764         platform_set_drvdata(pdev, mmc);
 765
 766         glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 767         glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
 768
 769         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
 770                         (u16)(host->data_mem->start));
 771         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
 772                         (u16)(host->data_mem->start >> 16));
 773
 774         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
 775                         (u16)(host->data_mem->start));
 776         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
 777                         (u16)(host->data_mem->start >> 16));
 778
 779         setup_timer(&host->disable_timer, glamo_mci_disable_timer,
 780                                 (unsigned long)host);
 781
 782         if ((ret = mmc_add_host(mmc))) {
 783                 dev_err(&pdev->dev, "failed to add mmc host.\n");
 784                 goto probe_freeirq;
 785         }
 786
 787         dev_info(&pdev->dev,"initialisation done.\n");
 788         return 0;
 789
 790 probe_freeirq:
 791         free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 792 probe_iounmap_data:
 793         iounmap(host->data_base);
 794 probe_free_mem_region_data:
 795         release_mem_region(host->data_mem->start, resource_size(host->data_mem));
 796 probe_iounmap_mmio:
 797         iounmap(host->mmio_base);
 798 probe_free_mem_region_mmio:
 799         release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
 800 probe_regulator_put:
 801         regulator_put(host->regulator);
 802 probe_free_host:
 803         mmc_free_host(mmc);
 804 probe_out:
 805         return ret;
 806 }
 807
 808 static int glamo_mci_remove(struct platform_device *pdev)
 809 {
 810         struct mmc_host *mmc = platform_get_drvdata(pdev);
 811         struct glamo_mci_host *host = mmc_priv(mmc);
 812
 813         free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
 814
 815         mmc_remove_host(mmc);
 816         iounmap(host->mmio_base);
 817         iounmap(host->data_base);
 818         release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
 819         release_mem_region(host->data_mem->start, resource_size(host->data_mem));
 820
 821         regulator_put(host->regulator);
 822
 823         mmc_free_host(mmc);
 824
 825         glamo_engine_disable(host->pdata->core, GLAMO_ENGINE_MMC);
 826         return 0;
 827 }
 828
 829
 830 #ifdef CONFIG_PM
 831
 832 static int glamo_mci_suspend(struct platform_device *dev, pm_message_t state)
 833 {
 834         struct mmc_host *mmc = platform_get_drvdata(dev);
 835         struct glamo_mci_host *host = mmc_priv(mmc);
 836         int ret;
 837
 838         cancel_work_sync(&host->irq_work);
 839
 840         ret = mmc_suspend_host(mmc, state);
 841         glamo_mci_clock_enable(host);
 842
 843         return ret;
 844 }
 845
 846 static int glamo_mci_resume(struct platform_device *dev)
 847 {
 848         struct mmc_host *mmc = platform_get_drvdata(dev);
 849         struct glamo_mci_host *host = mmc_priv(mmc);
 850         int ret;
 851
 852     glamo_engine_enable(host->pdata->core, GLAMO_ENGINE_MMC);
 853     glamo_engine_reset(host->pdata->core, GLAMO_ENGINE_MMC);
 854
 855         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
 856                         (u16)(host->data_mem->start));
 857         glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
 858                         (u16)(host->data_mem->start >> 16));
 859
 860         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
 861                         (u16)(host->data_mem->start));
 862         glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
 863                         (u16)(host->data_mem->start >> 16));
 864     mdelay(5);
 865
 866         ret = mmc_resume_host(host->mmc);
 867 /*      glamo_mci_clock_disable(host);*/
 868
 869         return 0;
 870 }
 871 EXPORT_SYMBOL_GPL(glamo_mci_resume);
 872
 873 #else /* CONFIG_PM */
 874 #define glamo_mci_suspend NULL
 875 #define glamo_mci_resume NULL
 876 #endif /* CONFIG_PM */
 877
 878
 879 static struct platform_driver glamo_mci_driver =
 880 {
 881         .driver.name    = "glamo-mci",
 882         .probe          = glamo_mci_probe,
 883         .remove         = glamo_mci_remove,
 884         .suspend        = glamo_mci_suspend,
 885         .resume         = glamo_mci_resume,
 886 };
 887
 888 static int __init glamo_mci_init(void)
 889 {
 890         platform_driver_register(&glamo_mci_driver);
 891         return 0;
 892 }
 893
 894 static void __exit glamo_mci_exit(void)
 895 {
 896         platform_driver_unregister(&glamo_mci_driver);
 897 }
 898
 899 module_init(glamo_mci_init);
 900 module_exit(glamo_mci_exit);
 901
 902 MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
 903 MODULE_LICENSE("GPL");
 904 MODULE_AUTHOR("Andy Green <andy@openmoko.com>");