target/linux/sunxi/patches-3.13/109-dt-sun6i-add-reset-ctrler.patch

   1 From f88dc0623908b574d9dcdae8815ccd0829fc6828 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Tue, 24 Sep 2013 11:10:41 +0300
   4 Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI
   5
   6 The A31 has a reset controller IP that maintains a few other IPs in
   7 reset, among which we can find the UARTs, high speed timers or the I2C.
   8 Now that we have support for them, add the reset controllers to the DTSI.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
  12 ---
  13  arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
  14  1 file changed, 24 insertions(+)
  15
  16 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
  17 index 7f5878c..97966b0 100644
  18 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  19 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  20 @@ -212,6 +212,24 @@
  21                         };
  22                 };
  23
  24 +               ahb1_rst: reset@01c202c0 {
  25 +                       #reset-cells = <1>;
  26 +                       compatible = "allwinner,sun6i-a31-ahb1-reset";
  27 +                       reg = <0x01c202c0 0xc>;
  28 +               };
  29 +
  30 +               apb1_rst: reset@01c202d0 {
  31 +                       #reset-cells = <1>;
  32 +                       compatible = "allwinner,sun6i-a31-clock-reset";
  33 +                       reg = <0x01c202d0 0x4>;
  34 +               };
  35 +
  36 +               apb2_rst: reset@01c202d8 {
  37 +                       #reset-cells = <1>;
  38 +                       compatible = "allwinner,sun6i-a31-clock-reset";
  39 +                       reg = <0x01c202d8 0x4>;
  40 +               };
  41 +
  42                 timer@01c20c00 {
  43                         compatible = "allwinner,sun4i-timer";
  44                         reg = <0x01c20c00 0xa0>;
  45 @@ -235,6 +253,7 @@
  46                         reg-shift = <2>;
  47                         reg-io-width = <4>;
  48                         clocks = <&apb2_gates 16>;
  49 +                       resets = <&apb2_rst 16>;
  50                         status = "disabled";
  51                 };
  52
  53 @@ -245,6 +264,7 @@
  54                         reg-shift = <2>;
  55                         reg-io-width = <4>;
  56                         clocks = <&apb2_gates 17>;
  57 +                       resets = <&apb2_rst 17>;
  58                         status = "disabled";
  59                 };
  60
  61 @@ -255,6 +275,7 @@
  62                         reg-shift = <2>;
  63                         reg-io-width = <4>;
  64                         clocks = <&apb2_gates 18>;
  65 +                       resets = <&apb2_rst 18>;
  66                         status = "disabled";
  67                 };
  68
  69 @@ -265,6 +286,7 @@
  70                         reg-shift = <2>;
  71                         reg-io-width = <4>;
  72                         clocks = <&apb2_gates 19>;
  73 +                       resets = <&apb2_rst 19>;
  74                         status = "disabled";
  75                 };
  76
  77 @@ -275,6 +297,7 @@
  78                         reg-shift = <2>;
  79                         reg-io-width = <4>;
  80                         clocks = <&apb2_gates 20>;
  81 +                       resets = <&apb2_rst 20>;
  82                         status = "disabled";
  83                 };
  84
  85 @@ -285,6 +308,7 @@
  86                         reg-shift = <2>;
  87                         reg-io-width = <4>;
  88                         clocks = <&apb2_gates 21>;
  89 +                       resets = <&apb2_rst 21>;
  90                         status = "disabled";
  91                 };
  92
  93 --
  94 1.8.5.1
  95