target/linux/sunxi/patches-3.13/120-clk-sunxi-mod0.patch

   1 From bdc913d1ef5143a8728ae414fcb90f9ed87a58da Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Mon, 23 Dec 2013 00:32:39 -0300
   4 Subject: [PATCH] clk: sunxi: mod0 support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This commit implements support for the "module 0" type of clocks, as
  10 used by MMC, IR, NAND, SATA and other components.
  11
  12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  13 Acked-by: Mike Turquette <mturquette@linaro.org>
  14 ---
  15  Documentation/devicetree/bindings/clock/sunxi.txt |  5 +-
  16  drivers/clk/sunxi/clk-sunxi.c                     | 57 +++++++++++++++++++++++
  17  2 files changed, 61 insertions(+), 1 deletion(-)
  18
  19 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
  20 index 80b2a39..46d8433 100644
  21 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  22 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  23 @@ -35,10 +35,13 @@ Required properties:
  24         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
  25         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  26         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  27 +       "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
  28
  29  Required properties for all clocks:
  30  - reg : shall be the control register address for the clock.
  31 -- clocks : shall be the input parent clock(s) phandle for the clock
  32 +- clocks : shall be the input parent clock(s) phandle for the clock. For
  33 +       multiplexed clocks, the list order must match the hardware
  34 +       programming order.
  35  - #clock-cells : from common clock binding; shall be set to 0 except for
  36         "allwinner,*-gates-clk" where it shall be set to 1
  37
  38 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
  39 index 649d7c3..af99b57 100644
  40 --- a/drivers/clk/sunxi/clk-sunxi.c
  41 +++ b/drivers/clk/sunxi/clk-sunxi.c
  42 @@ -295,6 +295,47 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
  43
  44
  45  /**
  46 + * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
  47 + * MMC rate is calculated as follows
  48 + * rate = (parent_rate >> p) / (m + 1);
  49 + */
  50 +
  51 +static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
  52 +                                  u8 *n, u8 *k, u8 *m, u8 *p)
  53 +{
  54 +       u8 div, calcm, calcp;
  55 +
  56 +       /* These clocks can only divide, so we will never be able to achieve
  57 +        * frequencies higher than the parent frequency */
  58 +       if (*freq > parent_rate)
  59 +               *freq = parent_rate;
  60 +
  61 +       div = parent_rate / *freq;
  62 +
  63 +       if (div < 16)
  64 +               calcp = 0;
  65 +       else if (div / 2 < 16)
  66 +               calcp = 1;
  67 +       else if (div / 4 < 16)
  68 +               calcp = 2;
  69 +       else
  70 +               calcp = 3;
  71 +
  72 +       calcm = DIV_ROUND_UP(div, 1 << calcp);
  73 +
  74 +       *freq = (parent_rate >> calcp) / calcm;
  75 +
  76 +       /* we were called to round the frequency, we can now return */
  77 +       if (n == NULL)
  78 +               return;
  79 +
  80 +       *m = calcm - 1;
  81 +       *p = calcp;
  82 +}
  83 +
  84 +
  85 +
  86 +/**
  87   * sunxi_factors_clk_setup() - Setup function for factor clocks
  88   */
  89
  90 @@ -341,6 +382,14 @@ struct factors_data {
  91         .pwidth = 2,
  92  };
  93
  94 +/* user manual says "n" but it's really "p" */
  95 +static struct clk_factors_config sun4i_mod0_config = {
  96 +       .mshift = 0,
  97 +       .mwidth = 4,
  98 +       .pshift = 16,
  99 +       .pwidth = 2,
 100 +};
 101 +
 102  static const struct factors_data sun4i_pll1_data __initconst = {
 103         .enable = 31,
 104         .table = &sun4i_pll1_config,
 105 @@ -364,6 +413,13 @@ struct factors_data {
 106         .getter = sun4i_get_apb1_factors,
 107  };
 108
 109 +static const struct factors_data sun4i_mod0_data __initconst = {
 110 +       .enable = 31,
 111 +       .mux = 24,
 112 +       .table = &sun4i_mod0_config,
 113 +       .getter = sun4i_get_mod0_factors,
 114 +};
 115 +
 116  static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
 117                                                 const struct factors_data *data)
 118  {
 119 @@ -852,6 +908,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 120         {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
 121         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 122         {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 123 +       {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
 124         {}
 125  };
 126
 127 --
 128 1.8.5.1
 129