1 From bdc913d1ef5143a8728ae414fcb90f9ed87a58da Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Mon, 23 Dec 2013 00:32:39 -0300
4 Subject: [PATCH] clk: sunxi: mod0 support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit implements support for the "module 0" type of clocks, as
10 used by MMC, IR, NAND, SATA and other components.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
13 Acked-by: Mike Turquette <mturquette@linaro.org>
15 Documentation/devicetree/bindings/clock/sunxi.txt | 5 +-
16 drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
17 2 files changed, 61 insertions(+), 1 deletion(-)
19 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
20 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
21 @@ -35,10 +35,13 @@ Required properties:
22 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
23 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
24 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
25 + "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
27 Required properties for all clocks:
28 - reg : shall be the control register address for the clock.
29 -- clocks : shall be the input parent clock(s) phandle for the clock
30 +- clocks : shall be the input parent clock(s) phandle for the clock. For
31 + multiplexed clocks, the list order must match the hardware
33 - #clock-cells : from common clock binding; shall be set to 0 except for
34 "allwinner,*-gates-clk" where it shall be set to 1
36 --- a/drivers/clk/sunxi/clk-sunxi.c
37 +++ b/drivers/clk/sunxi/clk-sunxi.c
38 @@ -295,6 +295,47 @@ static void sun4i_get_apb1_factors(u32 *
42 + * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
43 + * MMC rate is calculated as follows
44 + * rate = (parent_rate >> p) / (m + 1);
47 +static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
48 + u8 *n, u8 *k, u8 *m, u8 *p)
50 + u8 div, calcm, calcp;
52 + /* These clocks can only divide, so we will never be able to achieve
53 + * frequencies higher than the parent frequency */
54 + if (*freq > parent_rate)
55 + *freq = parent_rate;
57 + div = parent_rate / *freq;
61 + else if (div / 2 < 16)
63 + else if (div / 4 < 16)
68 + calcm = DIV_ROUND_UP(div, 1 << calcp);
70 + *freq = (parent_rate >> calcp) / calcm;
72 + /* we were called to round the frequency, we can now return */
83 * sunxi_factors_clk_setup() - Setup function for factor clocks
86 @@ -341,6 +382,14 @@ static struct clk_factors_config sun4i_a
90 +/* user manual says "n" but it's really "p" */
91 +static struct clk_factors_config sun4i_mod0_config = {
98 static const struct factors_data sun4i_pll1_data __initconst = {
100 .table = &sun4i_pll1_config,
101 @@ -364,6 +413,13 @@ static const struct factors_data sun4i_a
102 .getter = sun4i_get_apb1_factors,
105 +static const struct factors_data sun4i_mod0_data __initconst = {
108 + .table = &sun4i_mod0_config,
109 + .getter = sun4i_get_mod0_factors,
112 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
113 const struct factors_data *data)
115 @@ -852,6 +908,7 @@ static const struct of_device_id clk_fac
116 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
117 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
118 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
119 + {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},