1 From 9a8d3f21c94099a2bcd79ac1684cc8020fd98df2 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Mon, 23 Dec 2013 00:32:42 -0300
4 Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds all the mod0 clocks available on A10 and A13. The list
10 has been constructed by looking at the Allwinner code release for A10S
13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
14 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
16 arch/arm/boot/dts/sun5i-a10s.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
17 arch/arm/boot/dts/sun5i-a13.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
18 2 files changed, 176 insertions(+)
20 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
21 index ca19362..96c7185 100644
22 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
23 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
25 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
26 "apb1_uart2", "apb1_uart3";
29 + nand_clk: clk@01c20080 {
31 + compatible = "allwinner,sun4i-mod0-clk";
32 + reg = <0x01c20080 0x4>;
33 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
34 + clock-output-names = "nand";
37 + ms_clk: clk@01c20084 {
39 + compatible = "allwinner,sun4i-mod0-clk";
40 + reg = <0x01c20084 0x4>;
41 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
42 + clock-output-names = "ms";
45 + mmc0_clk: clk@01c20088 {
47 + compatible = "allwinner,sun4i-mod0-clk";
48 + reg = <0x01c20088 0x4>;
49 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
50 + clock-output-names = "mmc0";
53 + mmc1_clk: clk@01c2008c {
55 + compatible = "allwinner,sun4i-mod0-clk";
56 + reg = <0x01c2008c 0x4>;
57 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
58 + clock-output-names = "mmc1";
61 + mmc2_clk: clk@01c20090 {
63 + compatible = "allwinner,sun4i-mod0-clk";
64 + reg = <0x01c20090 0x4>;
65 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
66 + clock-output-names = "mmc2";
69 + ts_clk: clk@01c20098 {
71 + compatible = "allwinner,sun4i-mod0-clk";
72 + reg = <0x01c20098 0x4>;
73 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
74 + clock-output-names = "ts";
77 + ss_clk: clk@01c2009c {
79 + compatible = "allwinner,sun4i-mod0-clk";
80 + reg = <0x01c2009c 0x4>;
81 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
82 + clock-output-names = "ss";
85 + spi0_clk: clk@01c200a0 {
87 + compatible = "allwinner,sun4i-mod0-clk";
88 + reg = <0x01c200a0 0x4>;
89 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
90 + clock-output-names = "spi0";
93 + spi1_clk: clk@01c200a4 {
95 + compatible = "allwinner,sun4i-mod0-clk";
96 + reg = <0x01c200a4 0x4>;
97 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
98 + clock-output-names = "spi1";
101 + spi2_clk: clk@01c200a8 {
102 + #clock-cells = <0>;
103 + compatible = "allwinner,sun4i-mod0-clk";
104 + reg = <0x01c200a8 0x4>;
105 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
106 + clock-output-names = "spi2";
109 + ir0_clk: clk@01c200b0 {
110 + #clock-cells = <0>;
111 + compatible = "allwinner,sun4i-mod0-clk";
112 + reg = <0x01c200b0 0x4>;
113 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
114 + clock-output-names = "ir0";
119 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
120 index 9ac706a..e2505d6 100644
121 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
122 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
124 clock-output-names = "apb1_i2c0", "apb1_i2c1",
125 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
128 + nand_clk: clk@01c20080 {
129 + #clock-cells = <0>;
130 + compatible = "allwinner,sun4i-mod0-clk";
131 + reg = <0x01c20080 0x4>;
132 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
133 + clock-output-names = "nand";
136 + ms_clk: clk@01c20084 {
137 + #clock-cells = <0>;
138 + compatible = "allwinner,sun4i-mod0-clk";
139 + reg = <0x01c20084 0x4>;
140 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
141 + clock-output-names = "ms";
144 + mmc0_clk: clk@01c20088 {
145 + #clock-cells = <0>;
146 + compatible = "allwinner,sun4i-mod0-clk";
147 + reg = <0x01c20088 0x4>;
148 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
149 + clock-output-names = "mmc0";
152 + mmc1_clk: clk@01c2008c {
153 + #clock-cells = <0>;
154 + compatible = "allwinner,sun4i-mod0-clk";
155 + reg = <0x01c2008c 0x4>;
156 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
157 + clock-output-names = "mmc1";
160 + mmc2_clk: clk@01c20090 {
161 + #clock-cells = <0>;
162 + compatible = "allwinner,sun4i-mod0-clk";
163 + reg = <0x01c20090 0x4>;
164 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
165 + clock-output-names = "mmc2";
168 + ts_clk: clk@01c20098 {
169 + #clock-cells = <0>;
170 + compatible = "allwinner,sun4i-mod0-clk";
171 + reg = <0x01c20098 0x4>;
172 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
173 + clock-output-names = "ts";
176 + ss_clk: clk@01c2009c {
177 + #clock-cells = <0>;
178 + compatible = "allwinner,sun4i-mod0-clk";
179 + reg = <0x01c2009c 0x4>;
180 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
181 + clock-output-names = "ss";
184 + spi0_clk: clk@01c200a0 {
185 + #clock-cells = <0>;
186 + compatible = "allwinner,sun4i-mod0-clk";
187 + reg = <0x01c200a0 0x4>;
188 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
189 + clock-output-names = "spi0";
192 + spi1_clk: clk@01c200a4 {
193 + #clock-cells = <0>;
194 + compatible = "allwinner,sun4i-mod0-clk";
195 + reg = <0x01c200a4 0x4>;
196 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
197 + clock-output-names = "spi1";
200 + spi2_clk: clk@01c200a8 {
201 + #clock-cells = <0>;
202 + compatible = "allwinner,sun4i-mod0-clk";
203 + reg = <0x01c200a8 0x4>;
204 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
205 + clock-output-names = "spi2";
208 + ir0_clk: clk@01c200b0 {
209 + #clock-cells = <0>;
210 + compatible = "allwinner,sun4i-mod0-clk";
211 + reg = <0x01c200b0 0x4>;
212 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
213 + clock-output-names = "ir0";