target/linux/sunxi/patches-3.13/170-2-mmc-simplify-clkdelay.patch

   1 From 40889884d53094fe9987a45f9df99fdf1f311910 Mon Sep 17 00:00:00 2001
   2 From: Hans de Goede <hdegoede@redhat.com>
   3 Date: Sun, 16 Feb 2014 10:47:51 +0100
   4 Subject: [PATCH] sunxi-mmc: Simplify clk delay setting
   5
   6 clk_sunxi_mmc_phase_control() does its own locking, so there is no need to
   7 lock at the host. Without the locking having a separate sunxi_mmc_set_clk_dly()
   8 makes no sense, so simply call clk_sunxi_mmc_phase_control() directly.
   9
  10 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  11 ---
  12  drivers/mmc/host/sunxi-mmc.c | 14 ++------------
  13  1 file changed, 2 insertions(+), 12 deletions(-)
  14
  15 diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
  16 index f33bc30..f4bfaf0 100644
  17 --- a/drivers/mmc/host/sunxi-mmc.c
  18 +++ b/drivers/mmc/host/sunxi-mmc.c
  19 @@ -420,17 +420,6 @@ static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
  20         }
  21  }
  22
  23 -static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
  24 -                                 u32 oclk_dly, u32 sclk_dly)
  25 -{
  26 -       unsigned long iflags;
  27 -       struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
  28 -
  29 -       spin_lock_irqsave(&smc_host->lock, iflags);
  30 -       clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
  31 -       spin_unlock_irqrestore(&smc_host->lock, iflags);
  32 -}
  33 -
  34  struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
  35         { MMC_CLK_400K, 0, 7 },
  36         { MMC_CLK_25M, 0, 5 },
  37 @@ -450,6 +439,7 @@ static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
  38         u32 sclk_dly;
  39         u32 temp;
  40         struct sunxi_mmc_clk_dly *dly = NULL;
  41 +       struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
  42
  43         newrate = clk_round_rate(smc_host->clk_mod, rate);
  44         if (smc_host->clk_mod_rate == newrate) {
  45 @@ -508,7 +498,7 @@ static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
  46                         sclk_dly--;
  47         }
  48
  49 -       sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
  50 +       clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
  51         sunxi_mmc_oclk_onoff(smc_host, 1);
  52
  53         /* oclk_onoff sets various irq status bits, clear these */
  54 --
  55 1.8.5.5
  56