1 From 7f94ebf35b017f1664e957857a7f36752e2577cd Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Wed, 5 Feb 2014 14:05:04 +0100
4 Subject: [PATCH] ARM: sun6i: dt: Add PLL6 and SPI module clocks
6 The module clocks in the A31 are still compatible with the A10 one. Add the SPI
7 module clocks and the PLL6 in the device tree to allow their use by the SPI
10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
12 arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
13 1 file changed, 37 insertions(+), 9 deletions(-)
15 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
16 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
22 - * This is a dummy clock, to be used as placeholder on
23 - * other mux clocks when a specific parent clock is not
24 - * yet implemented. It should be dropped when the driver
28 + pll6: clk@01c20028 {
30 - compatible = "fixed-clock";
31 - clock-frequency = <0>;
32 + compatible = "allwinner,sun6i-a31-pll6-clk";
33 + reg = <0x01c20028 0x4>;
35 + clock-output-names = "pll6";
40 "apb2_uart1", "apb2_uart2", "apb2_uart3",
41 "apb2_uart4", "apb2_uart5";
44 + spi0_clk: clk@01c200a0 {
46 + compatible = "allwinner,sun4i-mod0-clk";
47 + reg = <0x01c200a0 0x4>;
48 + clocks = <&osc24M>, <&pll6>;
49 + clock-output-names = "spi0";
52 + spi1_clk: clk@01c200a4 {
54 + compatible = "allwinner,sun4i-mod0-clk";
55 + reg = <0x01c200a4 0x4>;
56 + clocks = <&osc24M>, <&pll6>;
57 + clock-output-names = "spi1";
60 + spi2_clk: clk@01c200a8 {
62 + compatible = "allwinner,sun4i-mod0-clk";
63 + reg = <0x01c200a8 0x4>;
64 + clocks = <&osc24M>, <&pll6>;
65 + clock-output-names = "spi2";
68 + spi3_clk: clk@01c200ac {
70 + compatible = "allwinner,sun4i-mod0-clk";
71 + reg = <0x01c200ac 0x4>;
72 + clocks = <&osc24M>, <&pll6>;
73 + clock-output-names = "spi3";