1 From 266f79cef78cdf3545065a4786506eee0ae012b3 Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Mon, 3 Feb 2014 09:51:42 +0800
4 Subject: [PATCH] ARM: dts: sun5i: rename clock node names to clk@N
6 Device tree naming conventions state that node names should match
7 node function. Change fully functioning clock nodes to match and
8 add clock-output-names to all sunxi clock nodes.
10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 arch/arm/boot/dts/sun5i-a10s.dtsi | 30 ++++++++++++++++++++----------
14 arch/arm/boot/dts/sun5i-a13.dtsi | 30 ++++++++++++++++++++----------
15 2 files changed, 40 insertions(+), 20 deletions(-)
17 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
18 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
20 clock-frequency = <0>;
23 - osc24M: osc24M@01c20050 {
24 + osc24M: clk@01c20050 {
26 compatible = "allwinner,sun4i-osc-clk";
27 reg = <0x01c20050 0x4>;
28 clock-frequency = <24000000>;
29 + clock-output-names = "osc24M";
35 compatible = "fixed-clock";
36 clock-frequency = <32768>;
37 + clock-output-names = "osc32k";
40 - pll1: pll1@01c20000 {
41 + pll1: clk@01c20000 {
43 compatible = "allwinner,sun4i-pll1-clk";
44 reg = <0x01c20000 0x4>;
46 + clock-output-names = "pll1";
49 - pll4: pll4@01c20018 {
50 + pll4: clk@01c20018 {
52 compatible = "allwinner,sun4i-pll1-clk";
53 reg = <0x01c20018 0x4>;
55 + clock-output-names = "pll4";
58 - pll5: pll5@01c20020 {
59 + pll5: clk@01c20020 {
61 compatible = "allwinner,sun4i-pll5-clk";
62 reg = <0x01c20020 0x4>;
64 clock-output-names = "pll5_ddr", "pll5_other";
67 - pll6: pll6@01c20028 {
68 + pll6: clk@01c20028 {
70 compatible = "allwinner,sun4i-pll6-clk";
71 reg = <0x01c20028 0x4>;
73 compatible = "allwinner,sun4i-cpu-clk";
74 reg = <0x01c20054 0x4>;
75 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
76 + clock-output-names = "cpu";
81 compatible = "allwinner,sun4i-axi-clk";
82 reg = <0x01c20054 0x4>;
84 + clock-output-names = "axi";
87 - axi_gates: axi_gates@01c2005c {
88 + axi_gates: clk@01c2005c {
90 compatible = "allwinner,sun4i-axi-gates-clk";
91 reg = <0x01c2005c 0x4>;
93 compatible = "allwinner,sun4i-ahb-clk";
94 reg = <0x01c20054 0x4>;
96 + clock-output-names = "ahb";
99 - ahb_gates: ahb_gates@01c20060 {
100 + ahb_gates: clk@01c20060 {
102 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
103 reg = <0x01c20060 0x8>;
105 compatible = "allwinner,sun4i-apb0-clk";
106 reg = <0x01c20054 0x4>;
108 + clock-output-names = "apb0";
111 - apb0_gates: apb0_gates@01c20068 {
112 + apb0_gates: clk@01c20068 {
114 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
115 reg = <0x01c20068 0x4>;
117 compatible = "allwinner,sun4i-apb1-mux-clk";
118 reg = <0x01c20058 0x4>;
119 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
120 + clock-output-names = "apb1_mux";
123 apb1: apb1@01c20058 {
125 compatible = "allwinner,sun4i-apb1-clk";
126 reg = <0x01c20058 0x4>;
127 clocks = <&apb1_mux>;
128 + clock-output-names = "apb1";
131 - apb1_gates: apb1_gates@01c2006c {
132 + apb1_gates: clk@01c2006c {
134 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
135 reg = <0x01c2006c 0x4>;
136 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
137 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
139 clock-frequency = <0>;
142 - osc24M: osc24M@01c20050 {
143 + osc24M: clk@01c20050 {
145 compatible = "allwinner,sun4i-osc-clk";
146 reg = <0x01c20050 0x4>;
147 clock-frequency = <24000000>;
148 + clock-output-names = "osc24M";
154 compatible = "fixed-clock";
155 clock-frequency = <32768>;
156 + clock-output-names = "osc32k";
159 - pll1: pll1@01c20000 {
160 + pll1: clk@01c20000 {
162 compatible = "allwinner,sun4i-pll1-clk";
163 reg = <0x01c20000 0x4>;
165 + clock-output-names = "pll1";
168 - pll4: pll4@01c20018 {
169 + pll4: clk@01c20018 {
171 compatible = "allwinner,sun4i-pll1-clk";
172 reg = <0x01c20018 0x4>;
174 + clock-output-names = "pll4";
177 - pll5: pll5@01c20020 {
178 + pll5: clk@01c20020 {
180 compatible = "allwinner,sun4i-pll5-clk";
181 reg = <0x01c20020 0x4>;
183 clock-output-names = "pll5_ddr", "pll5_other";
186 - pll6: pll6@01c20028 {
187 + pll6: clk@01c20028 {
189 compatible = "allwinner,sun4i-pll6-clk";
190 reg = <0x01c20028 0x4>;
192 compatible = "allwinner,sun4i-cpu-clk";
193 reg = <0x01c20054 0x4>;
194 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
195 + clock-output-names = "cpu";
200 compatible = "allwinner,sun4i-axi-clk";
201 reg = <0x01c20054 0x4>;
203 + clock-output-names = "axi";
206 - axi_gates: axi_gates@01c2005c {
207 + axi_gates: clk@01c2005c {
209 compatible = "allwinner,sun4i-axi-gates-clk";
210 reg = <0x01c2005c 0x4>;
212 compatible = "allwinner,sun4i-ahb-clk";
213 reg = <0x01c20054 0x4>;
215 + clock-output-names = "ahb";
218 - ahb_gates: ahb_gates@01c20060 {
219 + ahb_gates: clk@01c20060 {
221 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
222 reg = <0x01c20060 0x8>;
224 compatible = "allwinner,sun4i-apb0-clk";
225 reg = <0x01c20054 0x4>;
227 + clock-output-names = "apb0";
230 - apb0_gates: apb0_gates@01c20068 {
231 + apb0_gates: clk@01c20068 {
233 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
234 reg = <0x01c20068 0x4>;
236 compatible = "allwinner,sun4i-apb1-mux-clk";
237 reg = <0x01c20058 0x4>;
238 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
239 + clock-output-names = "apb1_mux";
242 apb1: apb1@01c20058 {
244 compatible = "allwinner,sun4i-apb1-clk";
245 reg = <0x01c20058 0x4>;
246 clocks = <&apb1_mux>;
247 + clock-output-names = "apb1";
250 - apb1_gates: apb1_gates@01c2006c {
251 + apb1_gates: clk@01c2006c {
253 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
254 reg = <0x01c2006c 0x4>;