1 From 8bd1bb3a670aae791c4b2e9ab13c92768233368a Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Mon, 3 Feb 2014 09:51:43 +0800
4 Subject: [PATCH] ARM: dts: sun6i: rename clock node names to clk@N
6 Device tree naming conventions state that node names should match
7 node function. Change fully functioning clock nodes to match and
8 add clock-output-names to all sunxi clock nodes.
10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++++++++++++++-----
14 1 file changed, 14 insertions(+), 5 deletions(-)
16 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
17 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
19 clock-frequency = <24000000>;
25 compatible = "fixed-clock";
26 clock-frequency = <32768>;
27 + clock-output-names = "osc32k";
30 - pll1: pll1@01c20000 {
31 + pll1: clk@01c20000 {
33 compatible = "allwinner,sun6i-a31-pll1-clk";
34 reg = <0x01c20000 0x4>;
36 + clock-output-names = "pll1";
43 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
44 + clock-output-names = "cpu";
49 compatible = "allwinner,sun4i-axi-clk";
50 reg = <0x01c20050 0x4>;
52 + clock-output-names = "axi";
55 ahb1_mux: ahb1_mux@01c20054 {
57 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
58 reg = <0x01c20054 0x4>;
59 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
60 + clock-output-names = "ahb1_mux";
65 compatible = "allwinner,sun4i-ahb-clk";
66 reg = <0x01c20054 0x4>;
68 + clock-output-names = "ahb1";
71 - ahb1_gates: ahb1_gates@01c20060 {
72 + ahb1_gates: clk@01c20060 {
74 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
75 reg = <0x01c20060 0x8>;
77 compatible = "allwinner,sun4i-apb0-clk";
78 reg = <0x01c20054 0x4>;
80 + clock-output-names = "apb1";
83 - apb1_gates: apb1_gates@01c20060 {
84 + apb1_gates: clk@01c20068 {
86 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
87 reg = <0x01c20068 0x4>;
89 compatible = "allwinner,sun4i-apb1-mux-clk";
90 reg = <0x01c20058 0x4>;
91 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
92 + clock-output-names = "apb2_mux";
97 compatible = "allwinner,sun6i-a31-apb2-div-clk";
98 reg = <0x01c20058 0x4>;
100 + clock-output-names = "apb2";
103 - apb2_gates: apb2_gates@01c2006c {
104 + apb2_gates: clk@01c2006c {
106 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
107 reg = <0x01c2006c 0x4>;