target/linux/sunxi/patches-3.14/146-1-spi-add-a31-spi.patch

   1 From 86cb7c7ab176112f8b0031dc7c8d19103ba52277 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Wed, 5 Feb 2014 14:05:05 +0100
   4 Subject: [PATCH] spi: sunxi: Add Allwinner A31 SPI controller driver
   5
   6 The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
   7 SoCs.
   8
   9 It supports DMA, but the driver only does PIO for now, and DMA will be
  10 supported eventually.
  11
  12 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 ---
  14  .../devicetree/bindings/spi/spi-sun6i.txt          |  24 +
  15  drivers/spi/Kconfig                                |   6 +
  16  drivers/spi/Makefile                               |   1 +
  17  drivers/spi/spi-sun6i.c                            | 483 +++++++++++++++++++++
  18  4 files changed, 514 insertions(+)
  19  create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt
  20  create mode 100644 drivers/spi/spi-sun6i.c
  21
  22 diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
  23 new file mode 100644
  24 index 0000000..21de73d
  25 --- /dev/null
  26 +++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
  27 @@ -0,0 +1,24 @@
  28 +Allwinner A31 SPI controller
  29 +
  30 +Required properties:
  31 +- compatible: Should be "allwinner,sun6i-a31-spi".
  32 +- reg: Should contain register location and length.
  33 +- interrupts: Should contain interrupt.
  34 +- clocks: phandle to the clocks feeding the SPI controller. Two are
  35 +          needed:
  36 +  - "ahb": the gated AHB parent clock
  37 +  - "mod": the parent module clock
  38 +- clock-names: Must contain the clock names described just above
  39 +- resets: phandle to the reset controller asserting this device in
  40 +          reset
  41 +
  42 +Example:
  43 +
  44 +spi1: spi@01c69000 {
  45 +       compatible = "allwinner,sun6i-a31-spi";
  46 +       reg = <0x01c69000 0x1000>;
  47 +       interrupts = <0 66 4>;
  48 +       clocks = <&ahb1_gates 21>, <&spi1_clk>;
  49 +       clock-names = "ahb", "mod";
  50 +       resets = <&ahb1_rst 21>;
  51 +};
  52 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  53 index 581ee2a..58530d3 100644
  54 --- a/drivers/spi/Kconfig
  55 +++ b/drivers/spi/Kconfig
  56 @@ -446,6 +446,12 @@ config SPI_SIRF
  57         help
  58           SPI driver for CSR SiRFprimaII SoCs
  59
  60 +config SPI_SUN6I
  61 +       tristate "Allwinner A31 SPI controller"
  62 +       depends on ARCH_SUNXI || COMPILE_TEST
  63 +       help
  64 +         This enables using the SPI controller on the Allwinner A31 SoCs.
  65 +
  66  config SPI_MXS
  67         tristate "Freescale MXS SPI controller"
  68         depends on ARCH_MXS
  69 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  70 index 95af48d..13b6ccf9 100644
  71 --- a/drivers/spi/Makefile
  72 +++ b/drivers/spi/Makefile
  73 @@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI)             += spi-sh-hspi.o
  74  obj-$(CONFIG_SPI_SH_MSIOF)             += spi-sh-msiof.o
  75  obj-$(CONFIG_SPI_SH_SCI)               += spi-sh-sci.o
  76  obj-$(CONFIG_SPI_SIRF)         += spi-sirf.o
  77 +obj-$(CONFIG_SPI_SUN6I)                        += spi-sun6i.o
  78  obj-$(CONFIG_SPI_TEGRA114)             += spi-tegra114.o
  79  obj-$(CONFIG_SPI_TEGRA20_SFLASH)       += spi-tegra20-sflash.o
  80  obj-$(CONFIG_SPI_TEGRA20_SLINK)                += spi-tegra20-slink.o
  81 diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
  82 new file mode 100644
  83 index 0000000..94d38d0
  84 --- /dev/null
  85 +++ b/drivers/spi/spi-sun6i.c
  86 @@ -0,0 +1,483 @@
  87 +/*
  88 + * Copyright (C) 2012 - 2014 Allwinner Tech
  89 + * Pan Nan <pannan@allwinnertech.com>
  90 + *
  91 + * Copyright (C) 2014 Maxime Ripard
  92 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  93 + *
  94 + * This program is free software; you can redistribute it and/or
  95 + * modify it under the terms of the GNU General Public License as
  96 + * published by the Free Software Foundation; either version 2 of
  97 + * the License, or (at your option) any later version.
  98 + */
  99 +
 100 +#include <linux/clk.h>
 101 +#include <linux/delay.h>
 102 +#include <linux/device.h>
 103 +#include <linux/interrupt.h>
 104 +#include <linux/io.h>
 105 +#include <linux/module.h>
 106 +#include <linux/platform_device.h>
 107 +#include <linux/pm_runtime.h>
 108 +#include <linux/reset.h>
 109 +#include <linux/workqueue.h>
 110 +
 111 +#include <linux/spi/spi.h>
 112 +
 113 +#define SUN6I_FIFO_DEPTH               128
 114 +
 115 +#define SUN6I_GBL_CTL_REG              0x04
 116 +#define SUN6I_GBL_CTL_BUS_ENABLE               BIT(0)
 117 +#define SUN6I_GBL_CTL_MASTER                   BIT(1)
 118 +#define SUN6I_GBL_CTL_TP                       BIT(7)
 119 +#define SUN6I_GBL_CTL_RST                      BIT(31)
 120 +
 121 +#define SUN6I_TFR_CTL_REG              0x08
 122 +#define SUN6I_TFR_CTL_CPHA                     BIT(0)
 123 +#define SUN6I_TFR_CTL_CPOL                     BIT(1)
 124 +#define SUN6I_TFR_CTL_SPOL                     BIT(2)
 125 +#define SUN6I_TFR_CTL_CS_MASK                  0x3
 126 +#define SUN6I_TFR_CTL_CS(cs)                   (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4)
 127 +#define SUN6I_TFR_CTL_CS_MANUAL                        BIT(6)
 128 +#define SUN6I_TFR_CTL_CS_LEVEL                 BIT(7)
 129 +#define SUN6I_TFR_CTL_DHB                      BIT(8)
 130 +#define SUN6I_TFR_CTL_FBS                      BIT(12)
 131 +#define SUN6I_TFR_CTL_XCH                      BIT(31)
 132 +
 133 +#define SUN6I_INT_CTL_REG              0x10
 134 +#define SUN6I_INT_CTL_RF_OVF                   BIT(8)
 135 +#define SUN6I_INT_CTL_TC                       BIT(12)
 136 +
 137 +#define SUN6I_INT_STA_REG              0x14
 138 +
 139 +#define SUN6I_FIFO_CTL_REG             0x18
 140 +#define SUN6I_FIFO_CTL_RF_RST                  BIT(15)
 141 +#define SUN6I_FIFO_CTL_TF_RST                  BIT(31)
 142 +
 143 +#define SUN6I_FIFO_STA_REG             0x1c
 144 +#define SUN6I_FIFO_STA_RF_CNT_MASK             0x7f
 145 +#define SUN6I_FIFO_STA_RF_CNT_BITS             0
 146 +#define SUN6I_FIFO_STA_TF_CNT_MASK             0x7f
 147 +#define SUN6I_FIFO_STA_TF_CNT_BITS             16
 148 +
 149 +#define SUN6I_CLK_CTL_REG              0x24
 150 +#define SUN6I_CLK_CTL_CDR2_MASK                        0xff
 151 +#define SUN6I_CLK_CTL_CDR2(div)                        (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
 152 +#define SUN6I_CLK_CTL_CDR1_MASK                        0xf
 153 +#define SUN6I_CLK_CTL_CDR1(div)                        (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
 154 +#define SUN6I_CLK_CTL_DRS                      BIT(12)
 155 +
 156 +#define SUN6I_BURST_CNT_REG            0x30
 157 +#define SUN6I_BURST_CNT(cnt)                   ((cnt) & 0xffffff)
 158 +
 159 +#define SUN6I_XMIT_CNT_REG             0x34
 160 +#define SUN6I_XMIT_CNT(cnt)                    ((cnt) & 0xffffff)
 161 +
 162 +#define SUN6I_BURST_CTL_CNT_REG                0x38
 163 +#define SUN6I_BURST_CTL_CNT_STC(cnt)           ((cnt) & 0xffffff)
 164 +
 165 +#define SUN6I_TXDATA_REG               0x200
 166 +#define SUN6I_RXDATA_REG               0x300
 167 +
 168 +struct sun6i_spi {
 169 +       struct spi_master       *master;
 170 +       void __iomem            *base_addr;
 171 +       struct clk              *hclk;
 172 +       struct clk              *mclk;
 173 +       struct reset_control    *rstc;
 174 +
 175 +       struct completion       done;
 176 +
 177 +       const u8                *tx_buf;
 178 +       u8                      *rx_buf;
 179 +       int                     len;
 180 +};
 181 +
 182 +static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
 183 +{
 184 +       return readl(sspi->base_addr + reg);
 185 +}
 186 +
 187 +static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
 188 +{
 189 +       writel(value, sspi->base_addr + reg);
 190 +}
 191 +
 192 +static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
 193 +{
 194 +       u32 reg, cnt;
 195 +       u8 byte;
 196 +
 197 +       /* See how much data is available */
 198 +       reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 199 +       reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
 200 +       cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
 201 +
 202 +       if (len > cnt)
 203 +               len = cnt;
 204 +
 205 +       while (len--) {
 206 +               byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
 207 +               if (sspi->rx_buf)
 208 +                       *sspi->rx_buf++ = byte;
 209 +       }
 210 +}
 211 +
 212 +static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
 213 +{
 214 +       u8 byte;
 215 +
 216 +       if (len > sspi->len)
 217 +               len = sspi->len;
 218 +
 219 +       while (len--) {
 220 +               byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 221 +               writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
 222 +               sspi->len--;
 223 +       }
 224 +}
 225 +
 226 +static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
 227 +{
 228 +       struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
 229 +       u32 reg;
 230 +
 231 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 232 +       reg &= ~SUN6I_TFR_CTL_CS_MASK;
 233 +       reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
 234 +
 235 +       if (enable)
 236 +               reg |= SUN6I_TFR_CTL_CS_LEVEL;
 237 +       else
 238 +               reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
 239 +
 240 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 241 +}
 242 +
 243 +
 244 +static int sun6i_spi_transfer_one(struct spi_master *master,
 245 +                                 struct spi_device *spi,
 246 +                                 struct spi_transfer *tfr)
 247 +{
 248 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 249 +       unsigned int mclk_rate, div, timeout;
 250 +       unsigned int tx_len = 0;
 251 +       int ret = 0;
 252 +       u32 reg;
 253 +
 254 +       /* We don't support transfer larger than the FIFO */
 255 +       if (tfr->len > SUN6I_FIFO_DEPTH)
 256 +               return -EINVAL;
 257 +
 258 +       reinit_completion(&sspi->done);
 259 +       sspi->tx_buf = tfr->tx_buf;
 260 +       sspi->rx_buf = tfr->rx_buf;
 261 +       sspi->len = tfr->len;
 262 +
 263 +       /* Clear pending interrupts */
 264 +       sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
 265 +
 266 +       /* Reset FIFO */
 267 +       sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 268 +                       SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
 269 +
 270 +       /*
 271 +        * Setup the transfer control register: Chip Select,
 272 +        * polarities, etc.
 273 +        */
 274 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 275 +
 276 +       if (spi->mode & SPI_CPOL)
 277 +               reg |= SUN6I_TFR_CTL_CPOL;
 278 +       else
 279 +               reg &= ~SUN6I_TFR_CTL_CPOL;
 280 +
 281 +       if (spi->mode & SPI_CPHA)
 282 +               reg |= SUN6I_TFR_CTL_CPHA;
 283 +       else
 284 +               reg &= ~SUN6I_TFR_CTL_CPHA;
 285 +
 286 +       if (spi->mode & SPI_LSB_FIRST)
 287 +               reg |= SUN6I_TFR_CTL_FBS;
 288 +       else
 289 +               reg &= ~SUN6I_TFR_CTL_FBS;
 290 +
 291 +       /*
 292 +        * If it's a TX only transfer, we don't want to fill the RX
 293 +        * FIFO with bogus data
 294 +        */
 295 +       if (sspi->rx_buf)
 296 +               reg &= ~SUN6I_TFR_CTL_DHB;
 297 +       else
 298 +               reg |= SUN6I_TFR_CTL_DHB;
 299 +
 300 +       /* We want to control the chip select manually */
 301 +       reg |= SUN6I_TFR_CTL_CS_MANUAL;
 302 +
 303 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 304 +
 305 +       /* Ensure that we have a parent clock fast enough */
 306 +       mclk_rate = clk_get_rate(sspi->mclk);
 307 +       if (mclk_rate < (2 * spi->max_speed_hz)) {
 308 +               clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
 309 +               mclk_rate = clk_get_rate(sspi->mclk);
 310 +       }
 311 +
 312 +       /*
 313 +        * Setup clock divider.
 314 +        *
 315 +        * We have two choices there. Either we can use the clock
 316 +        * divide rate 1, which is calculated thanks to this formula:
 317 +        * SPI_CLK = MOD_CLK / (2 ^ cdr)
 318 +        * Or we can use CDR2, which is calculated with the formula:
 319 +        * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 320 +        * Wether we use the former or the latter is set through the
 321 +        * DRS bit.
 322 +        *
 323 +        * First try CDR2, and if we can't reach the expected
 324 +        * frequency, fall back to CDR1.
 325 +        */
 326 +       div = mclk_rate / (2 * spi->max_speed_hz);
 327 +       if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
 328 +               if (div > 0)
 329 +                       div--;
 330 +
 331 +               reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
 332 +       } else {
 333 +               div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
 334 +               reg = SUN6I_CLK_CTL_CDR1(div);
 335 +       }
 336 +
 337 +       sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
 338 +
 339 +       /* Setup the transfer now... */
 340 +       if (sspi->tx_buf)
 341 +               tx_len = tfr->len;
 342 +
 343 +       /* Setup the counters */
 344 +       sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
 345 +       sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
 346 +       sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
 347 +                       SUN6I_BURST_CTL_CNT_STC(tx_len));
 348 +
 349 +       /* Fill the TX FIFO */
 350 +       sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
 351 +
 352 +       /* Enable the interrupts */
 353 +       sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
 354 +
 355 +       /* Start the transfer */
 356 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 357 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
 358 +
 359 +       timeout = wait_for_completion_timeout(&sspi->done,
 360 +                                             msecs_to_jiffies(1000));
 361 +       if (!timeout) {
 362 +               ret = -ETIMEDOUT;
 363 +               goto out;
 364 +       }
 365 +
 366 +       sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
 367 +
 368 +out:
 369 +       sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
 370 +
 371 +       return ret;
 372 +}
 373 +
 374 +static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
 375 +{
 376 +       struct sun6i_spi *sspi = dev_id;
 377 +       u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
 378 +
 379 +       /* Transfer complete */
 380 +       if (status & SUN6I_INT_CTL_TC) {
 381 +               sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
 382 +               complete(&sspi->done);
 383 +               return IRQ_HANDLED;
 384 +       }
 385 +
 386 +       return IRQ_NONE;
 387 +}
 388 +
 389 +static int sun6i_spi_runtime_resume(struct device *dev)
 390 +{
 391 +       struct spi_master *master = dev_get_drvdata(dev);
 392 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 393 +       int ret;
 394 +
 395 +       ret = clk_prepare_enable(sspi->hclk);
 396 +       if (ret) {
 397 +               dev_err(dev, "Couldn't enable AHB clock\n");
 398 +               goto out;
 399 +       }
 400 +
 401 +       ret = clk_prepare_enable(sspi->mclk);
 402 +       if (ret) {
 403 +               dev_err(dev, "Couldn't enable module clock\n");
 404 +               goto err;
 405 +       }
 406 +
 407 +       ret = reset_control_deassert(sspi->rstc);
 408 +       if (ret) {
 409 +               dev_err(dev, "Couldn't deassert the device from reset\n");
 410 +               goto err2;
 411 +       }
 412 +
 413 +       sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
 414 +                       SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
 415 +
 416 +       return 0;
 417 +
 418 +err2:
 419 +       clk_disable_unprepare(sspi->mclk);
 420 +err:
 421 +       clk_disable_unprepare(sspi->hclk);
 422 +out:
 423 +       return ret;
 424 +}
 425 +
 426 +static int sun6i_spi_runtime_suspend(struct device *dev)
 427 +{
 428 +       struct spi_master *master = dev_get_drvdata(dev);
 429 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 430 +
 431 +       reset_control_assert(sspi->rstc);
 432 +       clk_disable_unprepare(sspi->mclk);
 433 +       clk_disable_unprepare(sspi->hclk);
 434 +
 435 +       return 0;
 436 +}
 437 +
 438 +static int sun6i_spi_probe(struct platform_device *pdev)
 439 +{
 440 +       struct spi_master *master;
 441 +       struct sun6i_spi *sspi;
 442 +       struct resource *res;
 443 +       int ret = 0, irq;
 444 +
 445 +       master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
 446 +       if (!master) {
 447 +               dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 448 +               return -ENOMEM;
 449 +       }
 450 +
 451 +       platform_set_drvdata(pdev, master);
 452 +       sspi = spi_master_get_devdata(master);
 453 +
 454 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 455 +       sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
 456 +       if (IS_ERR(sspi->base_addr)) {
 457 +               ret = PTR_ERR(sspi->base_addr);
 458 +               goto err_free_master;
 459 +       }
 460 +
 461 +       irq = platform_get_irq(pdev, 0);
 462 +       if (irq < 0) {
 463 +               dev_err(&pdev->dev, "No spi IRQ specified\n");
 464 +               ret = -ENXIO;
 465 +               goto err_free_master;
 466 +       }
 467 +
 468 +       ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
 469 +                              0, "sun6i-spi", sspi);
 470 +       if (ret) {
 471 +               dev_err(&pdev->dev, "Cannot request IRQ\n");
 472 +               goto err_free_master;
 473 +       }
 474 +
 475 +       sspi->master = master;
 476 +       master->set_cs = sun6i_spi_set_cs;
 477 +       master->transfer_one = sun6i_spi_transfer_one;
 478 +       master->num_chipselect = 4;
 479 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 480 +       master->dev.of_node = pdev->dev.of_node;
 481 +       master->auto_runtime_pm = true;
 482 +
 483 +       sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 484 +       if (IS_ERR(sspi->hclk)) {
 485 +               dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 486 +               ret = PTR_ERR(sspi->hclk);
 487 +               goto err_free_master;
 488 +       }
 489 +
 490 +       sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 491 +       if (IS_ERR(sspi->mclk)) {
 492 +               dev_err(&pdev->dev, "Unable to acquire module clock\n");
 493 +               ret = PTR_ERR(sspi->mclk);
 494 +               goto err_free_master;
 495 +       }
 496 +
 497 +       init_completion(&sspi->done);
 498 +
 499 +       sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
 500 +       if (IS_ERR(sspi->rstc)) {
 501 +               dev_err(&pdev->dev, "Couldn't get reset controller\n");
 502 +               ret = PTR_ERR(sspi->rstc);
 503 +               goto err_free_master;
 504 +       }
 505 +
 506 +       /*
 507 +        * This wake-up/shutdown pattern is to be able to have the
 508 +        * device woken up, even if runtime_pm is disabled
 509 +        */
 510 +       ret = sun6i_spi_runtime_resume(&pdev->dev);
 511 +       if (ret) {
 512 +               dev_err(&pdev->dev, "Couldn't resume the device\n");
 513 +               goto err_free_master;
 514 +       }
 515 +
 516 +       pm_runtime_set_active(&pdev->dev);
 517 +       pm_runtime_enable(&pdev->dev);
 518 +       pm_runtime_idle(&pdev->dev);
 519 +
 520 +       ret = devm_spi_register_master(&pdev->dev, master);
 521 +       if (ret) {
 522 +               dev_err(&pdev->dev, "cannot register SPI master\n");
 523 +               goto err_pm_disable;
 524 +       }
 525 +
 526 +       return 0;
 527 +
 528 +err_pm_disable:
 529 +       pm_runtime_disable(&pdev->dev);
 530 +       sun6i_spi_runtime_suspend(&pdev->dev);
 531 +err_free_master:
 532 +       spi_master_put(master);
 533 +       return ret;
 534 +}
 535 +
 536 +static int sun6i_spi_remove(struct platform_device *pdev)
 537 +{
 538 +       pm_runtime_disable(&pdev->dev);
 539 +
 540 +       return 0;
 541 +}
 542 +
 543 +static const struct of_device_id sun6i_spi_match[] = {
 544 +       { .compatible = "allwinner,sun6i-a31-spi", },
 545 +       {}
 546 +};
 547 +MODULE_DEVICE_TABLE(of, sun6i_spi_match);
 548 +
 549 +static const struct dev_pm_ops sun6i_spi_pm_ops = {
 550 +       .runtime_resume         = sun6i_spi_runtime_resume,
 551 +       .runtime_suspend        = sun6i_spi_runtime_suspend,
 552 +};
 553 +
 554 +static struct platform_driver sun6i_spi_driver = {
 555 +       .probe  = sun6i_spi_probe,
 556 +       .remove = sun6i_spi_remove,
 557 +       .driver = {
 558 +               .name           = "sun6i-spi",
 559 +               .owner          = THIS_MODULE,
 560 +               .of_match_table = sun6i_spi_match,
 561 +               .pm             = &sun6i_spi_pm_ops,
 562 +       },
 563 +};
 564 +module_platform_driver(sun6i_spi_driver);
 565 +
 566 +MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
 567 +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 568 +MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
 569 +MODULE_LICENSE("GPL");
 570 --
 571 2.0.3
 572