target/linux/sunxi/patches-3.14/183-clk-sunxi-add-usb-clockreg-defs.patch

   1 From c61dfeb17581d32360a817ba40636aaed85caade Mon Sep 17 00:00:00 2001
   2 From: Roman Byshko <rbyshko@gmail.com>
   3 Date: Fri, 7 Feb 2014 16:21:50 +0100
   4 Subject: [PATCH] clk: sunxi: Add USB clock register defintions
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Add register definitions for the usb-clk register found on sun4i, sun5i and
  10 sun7i SoCs.
  11
  12 Signed-off-by: Roman Byshko <rbyshko@gmail.com>
  13 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  14 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  15 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  16 ---
  17  Documentation/devicetree/bindings/clock/sunxi.txt |  5 +++++
  18  drivers/clk/sunxi/clk-sunxi.c                     | 12 ++++++++++++
  19  2 files changed, 17 insertions(+)
  20
  21 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
  22 index 0cf679b..ca2b692 100644
  23 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  24 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  25 @@ -37,6 +37,8 @@ Required properties:
  26         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  27         "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
  28         "allwinner,sun7i-a20-out-clk" - for the external output clocks
  29 +       "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
  30 +       "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
  31
  32  Required properties for all clocks:
  33  - reg : shall be the control register address for the clock.
  34 @@ -50,6 +52,9 @@ Required properties for all clocks:
  35         If the clock module only has one output, the name shall be the
  36         module name.
  37
  38 +And "allwinner,*-usb-clk" clocks also require:
  39 +- reset-cells : shall be set to 1
  40 +
  41  Clock consumers should specify the desired clocks they use with a
  42  "clocks" phandle cell. Consumers that are using a gated clock should
  43  provide an additional ID in their clock property. This ID is the
  44 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
  45 index 23beb6e..a779c31 100644
  46 --- a/drivers/clk/sunxi/clk-sunxi.c
  47 +++ b/drivers/clk/sunxi/clk-sunxi.c
  48 @@ -816,6 +816,16 @@ static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
  49         .mask = { 0xff80ff },
  50  };
  51
  52 +static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
  53 +       .mask = {0x1C0},
  54 +       .reset_mask = 0x07,
  55 +};
  56 +
  57 +static const struct gates_data sun5i_a13_usb_gates_data __initconst = {
  58 +       .mask = {0x140},
  59 +       .reset_mask = 0x03,
  60 +};
  61 +
  62  static void __init sunxi_gates_clk_setup(struct device_node *node,
  63                                          struct gates_data *data)
  64  {
  65 @@ -1107,6 +1117,8 @@ static const struct of_device_id clk_gates_match[] __initconst = {
  66         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
  67         {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
  68         {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
  69 +       {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
  70 +       {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
  71         {}
  72  };
  73
  74 --
  75 2.0.3
  76