1 --- a/drivers/mtd/nand/nand_ids.c
2 +++ b/drivers/mtd/nand/nand_ids.c
4 #define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
7 + * Hynix H27UBG8T2BTR timings
8 + * This chip has an exceptionally large tADL, which results in only supporting
9 + * ONFI timing mode 0. Using these timings, the clock can be raised from
12 +const struct nand_sdr_timings hynix_h27ubg8t2btr_sdr_timing = {
28 + .tFEAT_max = 1000000,
30 + .tITC_max = 1000000,
39 + .tRST_max = 500000000,
51 * name, device ID, page size, chip size in MiB, eraseblock size, options
53 @@ -50,6 +93,10 @@ struct nand_flash_dev nand_flash_ids[] =
54 { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
55 SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
57 + {"H27UBG8T2BTR-BC 64G 3.3V 8-bit",
58 + { .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
59 + SZ_8K, SZ_4K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
60 + 0, &hynix_h27ubg8t2btr_sdr_timing },
62 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
63 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),