1 From 32bb743195e1e48c48fc5cefd7c6ecdce56046a3 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Fri, 18 Jul 2014 15:58:44 -0300
4 Subject: [PATCH] ARM: sunxi: Add PLL2 support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds the PLL2 definition to the sun4i, sun5i and sun7i
10 device trees. PLL2 is used to clock audio devices.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
13 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
15 arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++
16 arch/arm/boot/dts/sun5i.dtsi | 8 ++++++++
17 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
18 3 files changed, 24 insertions(+)
20 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
21 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
23 clock-output-names = "pll1";
26 + pll2: clk@01c20008 {
28 + compatible = "allwinner,sun4i-a10-b-pll2-clk";
29 + reg = <0x01c20008 0x4>;
31 + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
36 compatible = "allwinner,sun4i-a10-pll1-clk";
37 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
38 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
40 clock-output-names = "pll1";
43 + pll2: clk@01c20008 {
45 + compatible = "allwinner,sun4i-a10-b-pll2-clk";
46 + reg = <0x01c20008 0x4>;
48 + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
53 compatible = "allwinner,sun4i-a10-pll1-clk";
54 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
55 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
57 clock-output-names = "pll1";
60 + pll2: clk@01c20008 {
62 + compatible = "allwinner,sun4i-a10-b-pll2-clk";
63 + reg = <0x01c20008 0x4>;
65 + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8";
70 compatible = "allwinner,sun7i-a20-pll4-clk";