1 From 82f8582feef4c048ee7ef0155a71c23614a7856d Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Sat, 5 Dec 2015 21:16:44 +0800
4 Subject: [PATCH] ARM: dts: sun4i: Add DRAM gates
6 The DRAM gates controls direct memory access for some peripherals.
7 These peripherals include the display pipeline, so add the required
8 gates to the simplefb nodes as well.
10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++++++----
14 1 file changed, 32 insertions(+), 4 deletions(-)
16 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
17 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
20 allwinner,pipeline = "de_be0-lcd0-hdmi";
21 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
23 + <&ahb_gates 44>, <&dram_gates 26>;
29 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
30 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
31 - <&ahb_gates 44>, <&ahb_gates 46>;
32 + <&ahb_gates 44>, <&ahb_gates 46>,
33 + <&dram_gates 25>, <&dram_gates 26>;
39 allwinner,pipeline = "de_fe0-de_be0-lcd0";
40 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
42 + <&ahb_gates 46>, <&dram_gates 25>,
49 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
50 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
51 - <&ahb_gates 44>, <&ahb_gates 46>;
52 + <&ahb_gates 44>, <&ahb_gates 46>,
53 + <&dram_gates 25>, <&dram_gates 26>;
58 clock-output-names = "spi3";
61 + dram_gates: clk@01c20100 {
63 + compatible = "allwinner,sun4i-a10-dram-gates-clk";
64 + reg = <0x01c20100 0x4>;
66 + clock-indices = <0>,
75 + clock-output-names = "dram_ve",
76 + "dram_csi0", "dram_csi1",
79 + "dram_tve0", "dram_tve1",
81 + "dram_de_fe1", "dram_de_fe0",
82 + "dram_de_be0", "dram_de_be1",
83 + "dram_de_mp", "dram_ace";
86 codec_clk: clk@01c20140 {
88 compatible = "allwinner,sun4i-a10-codec-clk";