target/linux/sunxi/patches-4.4/110-clk-sunxi-add-ve-for-sun457i.patch

   1 From 3cdd9f5c4953465abb87ec757159cc0576ae6b0a Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Sat, 5 Dec 2015 21:16:43 +0800
   4 Subject: [PATCH] clk: sunxi: Add VE (Video Engine) module clock driver for
   5  sun[457]i
   6
   7 The video engine has its own special module clock, consisting of a clock
   8 gate, configurable dividers, and a reset control.
   9
  10 On later (sun[68]i) families, the reset control is moved out of this
  11 piece of hardware and grouped with reset controls of other peripherals.
  12
  13 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  14 Tested-by: Jens Kuske <jenskuske@gmail.com>
  15 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  16 ---
  17  Documentation/devicetree/bindings/clock/sunxi.txt |   4 +
  18  drivers/clk/sunxi/Makefile                        |   1 +
  19  drivers/clk/sunxi/clk-a10-ve.c                    | 171 ++++++++++++++++++++++
  20  3 files changed, 176 insertions(+)
  21  create mode 100644 drivers/clk/sunxi/clk-a10-ve.c
  22
  23 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
  24 index 014eab8..e59f57b 100644
  25 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  26 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  27 @@ -76,6 +76,7 @@ Required properties:
  28         "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
  29         "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
  30         "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
  31 +       "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
  32
  33  Required properties for all clocks:
  34  - reg : shall be the control register address for the clock.
  35 @@ -95,6 +96,9 @@ Required properties for all clocks:
  36  And "allwinner,*-usb-clk" clocks also require:
  37  - reset-cells : shall be set to 1
  38
  39 +The "allwinner,sun4i-a10-ve-clk" clock also requires:
  40 +- reset-cells : shall be set to 0
  41 +
  42  The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
  43  - #reset-cells : shall be set to 1
  44  - resets : shall be the reset control phandle for the mmc block.
  45 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
  46 index abf4916..1a909f9 100644
  47 --- a/drivers/clk/sunxi/Makefile
  48 +++ b/drivers/clk/sunxi/Makefile
  49 @@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o
  50  obj-y += clk-a10-hosc.o
  51  obj-y += clk-a10-mod1.o
  52  obj-y += clk-a10-pll2.o
  53 +obj-y += clk-a10-ve.o
  54  obj-y += clk-a20-gmac.o
  55  obj-y += clk-mod0.o
  56  obj-y += clk-simple-gates.o
  57 diff --git a/drivers/clk/sunxi/clk-a10-ve.c b/drivers/clk/sunxi/clk-a10-ve.c
  58 new file mode 100644
  59 index 0000000..044c171
  60 --- /dev/null
  61 +++ b/drivers/clk/sunxi/clk-a10-ve.c
  62 @@ -0,0 +1,171 @@
  63 +/*
  64 + * Copyright 2015 Chen-Yu Tsai
  65 + *
  66 + * Chen-Yu Tsai <wens@csie.org>
  67 + *
  68 + * This program is free software; you can redistribute it and/or modify
  69 + * it under the terms of the GNU General Public License as published by
  70 + * the Free Software Foundation; either version 2 of the License, or
  71 + * (at your option) any later version.
  72 + *
  73 + * This program is distributed in the hope that it will be useful,
  74 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  75 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  76 + * GNU General Public License for more details.
  77 + */
  78 +
  79 +#include <linux/clk-provider.h>
  80 +#include <linux/of.h>
  81 +#include <linux/of_address.h>
  82 +#include <linux/reset-controller.h>
  83 +#include <linux/slab.h>
  84 +#include <linux/spinlock.h>
  85 +
  86 +static DEFINE_SPINLOCK(ve_lock);
  87 +
  88 +#define SUN4I_VE_ENABLE                31
  89 +#define SUN4I_VE_DIVIDER_SHIFT 16
  90 +#define SUN4I_VE_DIVIDER_WIDTH 3
  91 +#define SUN4I_VE_RESET         0
  92 +
  93 +/**
  94 + * sunxi_ve_reset... - reset bit in ve clk registers handling
  95 + */
  96 +
  97 +struct ve_reset_data {
  98 +       void __iomem                    *reg;
  99 +       spinlock_t                      *lock;
 100 +       struct reset_controller_dev     rcdev;
 101 +};
 102 +
 103 +static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,
 104 +                                unsigned long id)
 105 +{
 106 +       struct ve_reset_data *data = container_of(rcdev,
 107 +                                                 struct ve_reset_data,
 108 +                                                 rcdev);
 109 +       unsigned long flags;
 110 +       u32 reg;
 111 +
 112 +       spin_lock_irqsave(data->lock, flags);
 113 +
 114 +       reg = readl(data->reg);
 115 +       writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
 116 +
 117 +       spin_unlock_irqrestore(data->lock, flags);
 118 +
 119 +       return 0;
 120 +}
 121 +
 122 +static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,
 123 +                                  unsigned long id)
 124 +{
 125 +       struct ve_reset_data *data = container_of(rcdev,
 126 +                                                 struct ve_reset_data,
 127 +                                                 rcdev);
 128 +       unsigned long flags;
 129 +       u32 reg;
 130 +
 131 +       spin_lock_irqsave(data->lock, flags);
 132 +
 133 +       reg = readl(data->reg);
 134 +       writel(reg | BIT(SUN4I_VE_RESET), data->reg);
 135 +
 136 +       spin_unlock_irqrestore(data->lock, flags);
 137 +
 138 +       return 0;
 139 +}
 140 +
 141 +static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,
 142 +                            const struct of_phandle_args *reset_spec)
 143 +{
 144 +       if (WARN_ON(reset_spec->args_count != 0))
 145 +               return -EINVAL;
 146 +
 147 +       return 0;
 148 +}
 149 +
 150 +static struct reset_control_ops sunxi_ve_reset_ops = {
 151 +       .assert         = sunxi_ve_reset_assert,
 152 +       .deassert       = sunxi_ve_reset_deassert,
 153 +};
 154 +
 155 +static void __init sun4i_ve_clk_setup(struct device_node *node)
 156 +{
 157 +       struct clk *clk;
 158 +       struct clk_divider *div;
 159 +       struct clk_gate *gate;
 160 +       struct ve_reset_data *reset_data;
 161 +       const char *parent;
 162 +       const char *clk_name = node->name;
 163 +       void __iomem *reg;
 164 +       int err;
 165 +
 166 +       reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 167 +       if (IS_ERR(reg))
 168 +               return;
 169 +
 170 +       div = kzalloc(sizeof(*div), GFP_KERNEL);
 171 +       if (!div)
 172 +               goto err_unmap;
 173 +
 174 +       gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 175 +       if (!gate)
 176 +               goto err_free_div;
 177 +
 178 +       of_property_read_string(node, "clock-output-names", &clk_name);
 179 +       parent = of_clk_get_parent_name(node, 0);
 180 +
 181 +       gate->reg = reg;
 182 +       gate->bit_idx = SUN4I_VE_ENABLE;
 183 +       gate->lock = &ve_lock;
 184 +
 185 +       div->reg = reg;
 186 +       div->shift = SUN4I_VE_DIVIDER_SHIFT;
 187 +       div->width = SUN4I_VE_DIVIDER_WIDTH;
 188 +       div->lock = &ve_lock;
 189 +
 190 +       clk = clk_register_composite(NULL, clk_name, &parent, 1,
 191 +                                    NULL, NULL,
 192 +                                    &div->hw, &clk_divider_ops,
 193 +                                    &gate->hw, &clk_gate_ops,
 194 +                                    CLK_SET_RATE_PARENT);
 195 +       if (IS_ERR(clk))
 196 +               goto err_free_gate;
 197 +
 198 +       err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 199 +       if (err)
 200 +               goto err_unregister_clk;
 201 +
 202 +       reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
 203 +       if (!reset_data)
 204 +               goto err_del_provider;
 205 +
 206 +       reset_data->reg = reg;
 207 +       reset_data->lock = &ve_lock;
 208 +       reset_data->rcdev.nr_resets = 1;
 209 +       reset_data->rcdev.ops = &sunxi_ve_reset_ops;
 210 +       reset_data->rcdev.of_node = node;
 211 +       reset_data->rcdev.of_xlate = sunxi_ve_of_xlate;
 212 +       reset_data->rcdev.of_reset_n_cells = 0;
 213 +       err = reset_controller_register(&reset_data->rcdev);
 214 +       if (err)
 215 +               goto err_free_reset;
 216 +
 217 +       return;
 218 +
 219 +err_free_reset:
 220 +       kfree(reset_data);
 221 +err_del_provider:
 222 +       of_clk_del_provider(node);
 223 +err_unregister_clk:
 224 +       clk_unregister(clk);
 225 +err_free_gate:
 226 +       kfree(gate);
 227 +err_free_div:
 228 +       kfree(div);
 229 +err_unmap:
 230 +       iounmap(reg);
 231 +}
 232 +CLK_OF_DECLARE(sun4i_ve, "allwinner,sun4i-a10-ve-clk",
 233 +              sun4i_ve_clk_setup);