5 * Copyright © 2009 Ubicom Inc. <www.ubicom.com>. All Rights Reserved.
7 * This file is part of the Ubicom32 Linux Kernel Port.
9 * The Ubicom32 Linux Kernel Port is free software: you can
10 * redistribute it and/or modify it under the terms of the GNU General
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16 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
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21 * see <http://www.gnu.org/licenses/>.
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33 #include <asm/ip5000.h>
34 #include <asm/thread.h>
37 #define PLIO_EXT_PORT RI
39 #define TRANSMIT_FIFO_WATERMARK 8
42 * PLIO non-blocking register definitions
48 unsigned rxfifo_thread_enable
: 1; /* allowed rxfifo thread enable */
50 unsigned rxfifo_thread
: 4; /* allowed rxfifo thread access */
52 unsigned br_thread
: 4; /* allowed blocking region thread access */
53 unsigned fn_reset
: 4; /* function reset bit vector */
54 unsigned rxfifo_sel
: 1; /* select between RXFIFO 0 and 1 */
55 unsigned fn_sel
: 3; /* select port function */
65 unsigned txfifo_uf
: 1; /* TXFIFO underflow */
66 unsigned txfifo_wm
: 1; /* TXFIFO watermark */
67 unsigned rxfifo_of
: 1; /* RXFIFO overflow */
68 unsigned rxfifo_wm
: 1; /* RXFIFO watermark */
70 unsigned lreg_int_addr_rd
: 1; /* read from specified LREG address */
71 unsigned lreg_int_addr_wr
: 1; /* write to specified LREG address */
72 unsigned extctl_int
: 4; /* synchronized external interrupts */
73 unsigned pfsm_int
: 1; /* state machine */
77 unsigned txfifo_reset
: 1; /* TXFIFO reset for int_set only */
78 unsigned rxfifo_reset
: 1; /* RXFIFO reset for int_set only */
80 unsigned idif_txfifo_flush
: 1; /* flush TXFIFO and idif_txfifo */
81 unsigned idif_rxfifo_flush
: 1; /* flush RXFIFO and idif_rxfifo */
82 unsigned pfsm_start
: 1; /* input to fsm */
83 unsigned txfifo_uf
: 1; /* TXFIFO underflow */
84 unsigned txfifo_wm
: 1; /* TXFIFO watermark */
85 unsigned rxfifo_of
: 1; /* RXFIFO overflow */
86 unsigned rxfifo_wm
: 1; /* RXFIFO watermark */
88 unsigned lreg_int_addr_rd
: 1; /* read from specified LREG address */
89 unsigned lreg_int_addr_wr
: 1; /* write to specified LREG address */
90 unsigned extctl_int
: 4; /* synchronized external interrupts */
91 unsigned pfsm_int
: 1; /* state machine */
103 PLIO_CLK_CORE
, /* CORE CLK */
104 PLIO_CLK_IO
, /* IO CLK */
105 PLIO_CLK_EXT
, /* EXT CLK */
109 unsigned edif_iaena_sel
: 1; /* Input Address Enable Select */
110 unsigned edif_iaclk_sel
: 1; /* Input Address Clock Select */
111 unsigned edif_iald_inv
: 1; /* Input Address Strobe Invert */
112 unsigned edif_idclk_sel
: 1; /* Input Data Clock Select */
113 unsigned edif_idld_inv
: 1; /* Input Data Strobe Invert */
114 unsigned edif_ds
: 3; /* specify IDR and ODR data shift */
115 unsigned edif_cmp_mode
: 1; /* configure IDR comparator output */
116 unsigned edif_idena_sel
: 1; /* Input Data Enable Select */
117 unsigned ecif_extclk_ena
: 1; /* plio_extctl output select */
118 unsigned idif_tx_fifo_cmd_sel
: 1; /* select pfsm_cmd data word position */
119 unsigned ptif_porti_cfg
: 2; /* select port I pin configuration */
120 unsigned ptif_portd_cfg
: 3; /* select port D pin configuration */
121 plio_port_mode_t ptif_port_mode
: 3; /* select other plio ports */
122 unsigned icif_clk_plio_ext_inv
: 1; /* invert external plio clock when set */
123 unsigned icif_rst_plio
: 1; /* reset plio function and io fifos */
124 plio_clk_src_t icif_clk_src_sel
: 2; /* select plio clock source */
125 unsigned pfsm_prog
: 1; /* enable pfsm programming */
126 unsigned pfsm_cmd
: 3; /* software input to pfsm */
131 unsigned idif_byteswap_tx
: 3; /* swap TXFIFO byte order */
132 unsigned idif_byteswap_rx
: 3; /* swap RXFIFO byte order */
134 unsigned lreg_ena
: 1; /* enable local register map */
135 unsigned lreg_addr_fifo_cmp_ena
: 1; /* enable a specific LREG address from/to TX/RX fifos */
136 unsigned lreg_addr_fifo_cmp
: 5; /* LREG address routed from/to TX/RX fifos */
138 unsigned dcod_iald_idld_sel
: 2; /* select address/data strobes */
139 unsigned dcod_rw_src_sel
: 1; /* select LREG strobe source */
140 unsigned dcod_rd_sel
: 5; /* select read strobe source */
141 unsigned dcod_wr_sel
: 5; /* select write strobe source */
142 unsigned dcod_rd_lvl
: 1; /* select active level of read strobe */
143 unsigned dcod_wr_lvl
: 1; /* select active level of read strobe */
147 unsigned icif_eclk_div
: 16; /* external plio clock divider */
148 unsigned icif_iclk_div
: 16; /* internal plio clock divider */
153 unsigned pfsm_state
: 5; /* current pfsm state */
158 unsigned lreg_r_int_addr
: 5;
160 unsigned lreg_w_int_addr
: 5;
161 unsigned lreg_w_int_data
: 8;
171 } plio_io_fifo_wm_t
, plio_io_fifo_lvl_t
;
174 /* plio blocking region register definitions
218 plio_grpsel_t grpsel
[4];
220 plio_cs_lut_t cs_lut
[4];
221 plio_extctl_t extctl_o_lut
[8];
233 PLIO_ECIF_CLK_OUT
= 9,
235 PLIO_ECIF_CLK_IN
= 8,
238 } plio_ecif_output_t
;
249 u32_t idr_addr_pos_mask
;
257 u32_t addr_rd_int_ena
;
258 u32_t addr_wr_int_ena
;
280 plio_io_function_t function
;
281 plio_gpio_t gpio_ctl
;
282 plio_gpio_t gpio_out
;
284 plio_intstat_t intstat
;
285 plio_intstat_t intmask
;
286 plio_intset_t intset
;
287 plio_intstat_t intclr
;
298 plio_io_fifo_wm_t fifo_wm
;
299 plio_io_fifo_lvl_t fifo_lvl
;
303 u32_t pfsm_sram
[256];
304 plio_config_t config
;
307 #define PLIO_NBR ((plio_nbr_t *)(PLIO_PORT))
308 #define PLIO_BR ((plio_br_t *)((PLIO_PORT + IO_PORT_BR_OFFSET)))
309 #define PEXT_NBR ((plio_nbr_t *)(PLIO_EXT_PORT))
311 extern void plio_init(const plio_fctl_t
*plio_fctl
, const plio_config_t
*plio_config
, const plio_sram_t plio_sram_cfg
[], int sram_cfg_size
);
313 #endif // __PLIO__H__