1 From d5814bdb661d3dac61422f8f69e459be884c9a9d Mon Sep 17 00:00:00 2001
2 From: Maarten ter Huurne <maarten@treewalker.org>
3 Date: Tue, 2 Aug 2011 10:49:28 +0200
4 Subject: [PATCH 06/21] MTD: NAND: JZ4740: Multi-bank support with
7 The platform data can now specify which external memory banks to probe
8 for NAND chips, and in which order. Banks that contain a NAND are used
9 and the other banks are freed.
11 Squashed version of development done in jz-2.6.38 branch.
12 Original patch by Lars-Peter Clausen with some bug fixes from me.
13 Thanks to Paul Cercueil for the initial autodetection patch.
15 arch/mips/include/asm/mach-jz4740/jz4740_nand.h | 4 +
16 arch/mips/jz4740/platform.c | 20 ++-
17 drivers/mtd/nand/jz4740_nand.c | 228 +++++++++++++++++++----
18 3 files changed, 215 insertions(+), 37 deletions(-)
20 --- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
21 +++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
23 #include <linux/mtd/nand.h>
24 #include <linux/mtd/partitions.h>
26 +#define JZ_NAND_NUM_BANKS 4
28 struct jz_nand_platform_data {
30 struct mtd_partition *partitions;
31 @@ -27,6 +29,8 @@ struct jz_nand_platform_data {
33 unsigned int busy_gpio;
35 + unsigned char banks[JZ_NAND_NUM_BANKS];
37 void (*ident_callback)(struct platform_device *, struct nand_chip *,
38 struct mtd_partition **, int *num_partitions);
40 --- a/arch/mips/jz4740/platform.c
41 +++ b/arch/mips/jz4740/platform.c
42 @@ -157,11 +157,29 @@ static struct resource jz4740_nand_resou
43 .flags = IORESOURCE_MEM,
49 .end = 0x180C0000 - 1,
50 .flags = IORESOURCE_MEM,
54 + .start = 0x14000000,
55 + .end = 0x140C0000 - 1,
56 + .flags = IORESOURCE_MEM,
60 + .start = 0x0C000000,
61 + .end = 0x0C0C0000 - 1,
62 + .flags = IORESOURCE_MEM,
66 + .start = 0x08000000,
67 + .end = 0x080C0000 - 1,
68 + .flags = IORESOURCE_MEM,
72 struct platform_device jz4740_nand_device = {
73 --- a/drivers/mtd/nand/jz4740_nand.c
74 +++ b/drivers/mtd/nand/jz4740_nand.c
77 #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
78 #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
79 +#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
81 -#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
82 #define JZ_NAND_MEM_CMD_OFFSET 0x08000
83 +#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
87 @@ -62,8 +63,11 @@ struct jz_nand {
91 - void __iomem *bank_base;
92 - struct resource *bank_mem;
93 + unsigned char banks[JZ_NAND_NUM_BANKS];
94 + void __iomem *bank_base[JZ_NAND_NUM_BANKS];
95 + struct resource *bank_mem[JZ_NAND_NUM_BANKS];
99 struct jz_nand_platform_data *pdata;
101 @@ -74,26 +78,50 @@ static inline struct jz_nand *mtd_to_jz_
102 return container_of(mtd, struct jz_nand, mtd);
105 +static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
107 + struct jz_nand *nand = mtd_to_jz_nand(mtd);
108 + struct nand_chip *chip = mtd->priv;
112 + ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
113 + ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
115 + if (chipnr == -1) {
118 + banknr = nand->banks[chipnr] - 1;
119 + chip->IO_ADDR_R = nand->bank_base[banknr];
120 + chip->IO_ADDR_W = nand->bank_base[banknr];
122 + writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
124 + nand->selected_bank = banknr;
127 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
129 struct jz_nand *nand = mtd_to_jz_nand(mtd);
130 struct nand_chip *chip = mtd->priv;
132 + void __iomem *bank_base = nand->bank_base[nand->selected_bank];
134 + BUG_ON(nand->selected_bank < 0);
136 if (ctrl & NAND_CTRL_CHANGE) {
137 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
139 - chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET;
140 + bank_base += JZ_NAND_MEM_ADDR_OFFSET;
141 else if (ctrl & NAND_CLE)
142 - chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET;
144 - chip->IO_ADDR_W = nand->bank_base;
145 + bank_base += JZ_NAND_MEM_CMD_OFFSET;
146 + chip->IO_ADDR_W = bank_base;
148 reg = readl(nand->base + JZ_REG_NAND_CTRL);
150 - reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
151 + reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
153 - reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
154 + reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
155 writel(reg, nand->base + JZ_REG_NAND_CTRL);
157 if (dat != NAND_CMD_NONE)
158 @@ -252,7 +280,7 @@ static int jz_nand_correct_ecc_rs(struct
161 static int jz_nand_ioremap_resource(struct platform_device *pdev,
162 - const char *name, struct resource **res, void __iomem **base)
163 + const char *name, struct resource **res, void *__iomem *base)
167 @@ -288,6 +316,90 @@ err:
171 +static inline void jz_nand_iounmap_resource(struct resource *res, void __iomem *base)
174 + release_mem_region(res->start, resource_size(res));
177 +static int __devinit jz_nand_detect_bank(struct platform_device *pdev, struct jz_nand *nand, unsigned char bank, size_t chipnr, uint8_t *nand_maf_id, uint8_t *nand_dev_id) {
183 + struct mtd_info *mtd = &nand->mtd;
184 + struct nand_chip *chip = &nand->chip;
186 + /* Request GPIO port. */
187 + gpio = JZ_GPIO_MEM_CS0 + bank - 1;
188 + sprintf(gpio_name, "NAND CS%d", bank);
189 + ret = gpio_request(gpio, gpio_name);
191 + dev_warn(&pdev->dev,
192 + "Failed to request %s gpio %d: %d\n",
193 + gpio_name, gpio, ret);
194 + goto notfound_gpio;
197 + /* Request I/O resource. */
198 + sprintf(res_name, "bank%d", bank);
199 + ret = jz_nand_ioremap_resource(pdev, res_name,
200 + &nand->bank_mem[bank - 1],
201 + &nand->bank_base[bank - 1]);
203 + goto notfound_resource;
205 + /* Enable chip in bank. */
206 + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
207 + ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
208 + ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
209 + writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
212 + /* Detect first chip. */
213 + ret = nand_scan_ident(mtd, 1, NULL);
217 + /* Retrieve the IDs from the first chip. */
218 + chip->select_chip(mtd, 0);
219 + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
220 + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
221 + *nand_maf_id = chip->read_byte(mtd);
222 + *nand_dev_id = chip->read_byte(mtd);
224 + /* Detect additional chip. */
225 + chip->select_chip(mtd, chipnr);
226 + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
227 + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
228 + if (*nand_maf_id != chip->read_byte(mtd)
229 + || *nand_dev_id != chip->read_byte(mtd)) {
234 + /* Update size of the MTD. */
236 + mtd->size += chip->chipsize;
239 + dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
243 + dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
244 + ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
245 + writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
246 + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
247 + jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
248 + nand->bank_base[bank - 1]);
255 static int __devinit jz_nand_probe(struct platform_device *pdev)
258 @@ -295,6 +407,8 @@ static int __devinit jz_nand_probe(struc
259 struct nand_chip *chip;
260 struct mtd_info *mtd;
261 struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
262 + size_t chipnr, bank_idx;
263 + uint8_t nand_maf_id = 0, nand_dev_id = 0;
265 nand = kzalloc(sizeof(*nand), GFP_KERNEL);
267 @@ -305,10 +419,6 @@ static int __devinit jz_nand_probe(struc
268 ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
271 - ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem,
274 - goto err_iounmap_mmio;
276 if (pdata && gpio_is_valid(pdata->busy_gpio)) {
277 ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
278 @@ -316,7 +426,7 @@ static int __devinit jz_nand_probe(struc
280 "Failed to request busy gpio %d: %d\n",
281 pdata->busy_gpio, ret);
282 - goto err_iounmap_mem;
283 + goto err_iounmap_mmio;
287 @@ -338,22 +448,51 @@ static int __devinit jz_nand_probe(struc
289 chip->chip_delay = 50;
290 chip->cmd_ctrl = jz_nand_cmd_ctrl;
291 + chip->select_chip = jz_nand_select_chip;
293 if (pdata && gpio_is_valid(pdata->busy_gpio))
294 chip->dev_ready = jz_nand_dev_ready;
296 - chip->IO_ADDR_R = nand->bank_base;
297 - chip->IO_ADDR_W = nand->bank_base;
300 platform_set_drvdata(pdev, nand);
302 - writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL);
304 - ret = nand_scan_ident(mtd, 1, NULL);
306 - dev_err(&pdev->dev, "Failed to scan nand\n");
307 - goto err_gpio_free;
308 + /* We are going to autodetect NAND chips in the banks specified in the
309 + * platform data. Although nand_scan_ident() can detect multiple chips,
310 + * it requires those chips to be numbered consecuitively, which is not
311 + * always the case for external memory banks. And a fixed chip-to-bank
312 + * mapping is not practical either, since for example Dingoo units
313 + * produced at different times have NAND chips in different banks.
316 + for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
317 + unsigned char bank;
319 + /* If there is no platform data, look for NAND in bank 1,
320 + * which is the most likely bank since it is the only one
321 + * that can be booted from.
323 + bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
326 + if (bank > JZ_NAND_NUM_BANKS) {
327 + dev_warn(&pdev->dev,
328 + "Skipping non-existing bank: %d\n", bank);
331 + /* The detection routine will directly or indirectly call
332 + * jz_nand_select_chip(), so nand->banks has to contain the
333 + * bank we're checking.
335 + nand->banks[chipnr] = bank;
336 + if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
337 + &nand_maf_id, &nand_dev_id) == 0)
340 + nand->banks[chipnr] = 0;
343 + dev_err(&pdev->dev, "No NAND chips found\n");
344 + goto err_gpio_busy;
347 if (pdata && pdata->ident_callback) {
348 @@ -363,8 +502,8 @@ static int __devinit jz_nand_probe(struc
350 ret = nand_scan_tail(mtd);
352 - dev_err(&pdev->dev, "Failed to scan nand\n");
353 - goto err_gpio_free;
354 + dev_err(&pdev->dev, "Failed to scan NAND\n");
355 + goto err_unclaim_banks;
358 ret = mtd_device_parse_register(mtd, NULL, 0,
359 @@ -381,14 +520,21 @@ static int __devinit jz_nand_probe(struc
363 - nand_release(&nand->mtd);
368 + unsigned char bank = nand->banks[chipnr];
369 + gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
370 + jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
371 + nand->bank_base[bank - 1]);
373 + writel(0, nand->base + JZ_REG_NAND_CTRL);
375 + if (pdata && gpio_is_valid(pdata->busy_gpio))
376 + gpio_free(pdata->busy_gpio);
377 platform_set_drvdata(pdev, NULL);
378 - gpio_free(pdata->busy_gpio);
380 - iounmap(nand->bank_base);
382 - iounmap(nand->base);
383 + jz_nand_iounmap_resource(nand->mem, nand->base);
387 @@ -397,16 +543,26 @@ err_free:
388 static int __devexit jz_nand_remove(struct platform_device *pdev)
390 struct jz_nand *nand = platform_get_drvdata(pdev);
391 + struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
394 nand_release(&nand->mtd);
396 /* Deassert and disable all chips */
397 writel(0, nand->base + JZ_REG_NAND_CTRL);
399 - iounmap(nand->bank_base);
400 - release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem));
401 - iounmap(nand->base);
402 - release_mem_region(nand->mem->start, resource_size(nand->mem));
403 + for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
404 + unsigned char bank = nand->banks[i];
406 + jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
407 + nand->bank_base[bank - 1]);
408 + gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
411 + if (pdata && gpio_is_valid(pdata->busy_gpio))
412 + gpio_free(pdata->busy_gpio);
414 + jz_nand_iounmap_resource(nand->mem, nand->base);
416 platform_set_drvdata(pdev, NULL);