+#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
+#define AR724X_PCI_CFG_SIZE 0x1000
+
+#define AR724X_PCI_REG_APP 0x00
+#define AR724X_PCI_REG_RESET 0x18
+#define AR724X_PCI_REG_INT_STATUS 0x4c
+#define AR724X_PCI_REG_INT_MASK 0x50
+
+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
+
+#define AR724X_PCI_INT_DEV0 BIT(14)
+
+static inline void ar724x_pci_wr(unsigned reg, u32 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ __raw_writel(val, base + reg);
+ iounmap(base);
+}
+
+static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ iounmap(base);
+}
+
+static inline u32 ar724x_pci_rr(unsigned reg)
+{
+ void __iomem *base;
+ u32 ret;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ ret = __raw_readl(base + reg);
+ iounmap(base);
+ return ret;
+}
+