- /*
- * WAR for the QUalcomm Atheros AP136 board.
- * It seems that RGMII TX/RX delay settings needs to be
- * applied for SGMII mode as well, The ethernet is not
- * reliable without this.
- */
- t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
- t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
- if (cfg->rxclk_delay_en)
- t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
- if (cfg->txclk_delay_en)
- t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
-
- if (cfg->sgmii_delay_en)
- t |= AR8327_PAD_SGMII_DELAY_EN;
-
- break;
-
- case AR8327_PAD_MAC2PHY_MII:
- t = AR8327_PAD_PHY_MII_EN;
- if (cfg->rxclk_sel)
- t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
- if (cfg->txclk_sel)
- t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
- break;
-
- case AR8327_PAD_MAC2PHY_GMII:
- t = AR8327_PAD_PHY_GMII_EN;
- if (cfg->pipe_rxclk_sel)
- t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
- if (cfg->rxclk_sel)
- t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
- if (cfg->txclk_sel)
- t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
- break;
-
- case AR8327_PAD_MAC_RGMII:
- t = AR8327_PAD_RGMII_EN;
- t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
- t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
- if (cfg->rxclk_delay_en)
- t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
- if (cfg->txclk_delay_en)
- t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
- break;
-
- case AR8327_PAD_PHY_GMII:
- t = AR8327_PAD_PHYX_GMII_EN;
- break;
-
- case AR8327_PAD_PHY_RGMII:
- t = AR8327_PAD_PHYX_RGMII_EN;
- break;
-
- case AR8327_PAD_PHY_MII:
- t = AR8327_PAD_PHYX_MII_EN;
- break;
- }
-
- return t;
-}
-
-static void
-ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
-{
- switch (priv->chip_rev) {
- case 1:
- /* For 100M waveform */
- ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
- /* Turn on Gigabit clock */
- ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
- break;
-
- case 2:
- ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
- ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
- /* fallthrough */
- case 4:
- ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
- ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
-
- ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
- ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
- ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
- break;
- }
-}
-
-static u32
-ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
-{
- u32 t;
-
- if (!cfg->force_link)
- return AR8216_PORT_STATUS_LINK_AUTO;
-
- t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
- t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
- t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
- t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
-
- switch (cfg->speed) {
- case AR8327_PORT_SPEED_10:
- t |= AR8216_PORT_SPEED_10M;
- break;
- case AR8327_PORT_SPEED_100:
- t |= AR8216_PORT_SPEED_100M;
- break;
- case AR8327_PORT_SPEED_1000:
- t |= AR8216_PORT_SPEED_1000M;
- break;
- }
-
- return t;
-}
-
-#define AR8327_LED_ENTRY(_num, _reg, _shift) \
- [_num] = { .reg = (_reg), .shift = (_shift) }
-
-static const struct ar8327_led_entry
-ar8327_led_map[AR8327_NUM_LEDS] = {
- AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
- AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
- AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
-
- AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
- AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
- AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
-
- AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
- AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
- AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
-
- AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
- AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
- AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
-
- AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
- AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
- AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
-};
-
-static void
-ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
- enum ar8327_led_pattern pattern)
-{
- const struct ar8327_led_entry *entry;
-
- entry = &ar8327_led_map[led_num];
- ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
- (3 << entry->shift), pattern << entry->shift);
-}
-
-static void
-ar8327_led_work_func(struct work_struct *work)
-{
- struct ar8327_led *aled;
- u8 pattern;
-
- aled = container_of(work, struct ar8327_led, led_work);
-
- spin_lock(&aled->lock);
- pattern = aled->pattern;
- spin_unlock(&aled->lock);
-
- ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
- pattern);
-}
-
-static void
-ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
-{
- if (aled->pattern == pattern)
- return;
-
- aled->pattern = pattern;
- schedule_work(&aled->led_work);
-}
-
-static inline struct ar8327_led *
-led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
-{
- return container_of(led_cdev, struct ar8327_led, cdev);
-}
-
-static int
-ar8327_led_blink_set(struct led_classdev *led_cdev,
- unsigned long *delay_on,
- unsigned long *delay_off)
-{
- struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
-
- if (*delay_on == 0 && *delay_off == 0) {
- *delay_on = 125;
- *delay_off = 125;
- }
-
- if (*delay_on != 125 || *delay_off != 125) {
- /*
- * The hardware only supports blinking at 4Hz. Fall back
- * to software implementation in other cases.
- */
- return -EINVAL;
- }
-
- spin_lock(&aled->lock);
-
- aled->enable_hw_mode = false;
- ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);