+@@ -103,6 +103,41 @@ static int dwc3_get_dr_mode(struct dwc3
+ static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
+ static int dwc3_event_buffers_setup(struct dwc3 *dwc);
+
++/*
++ * dwc3_power_of_all_roothub_ports - Power off all Root hub ports
++ * @dwc3: Pointer to our controller context structure
++ */
++static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
++{
++ int i, port_num;
++ u32 reg, op_regs_base, offset;
++ void __iomem *xhci_regs;
++
++ /* xhci regs is not mapped yet, do it temperary here */
++ if (dwc->xhci_resources[0].start) {
++ xhci_regs = ioremap(dwc->xhci_resources[0].start,
++ DWC3_XHCI_REGS_END);
++ if (IS_ERR(xhci_regs)) {
++ dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
++ return;
++ }
++
++ op_regs_base = HC_LENGTH(readl(xhci_regs));
++ reg = readl(xhci_regs + XHCI_HCSPARAMS1);
++ port_num = HCS_MAX_PORTS(reg);
++
++ for (i = 1; i <= port_num; i++) {
++ offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
++ reg = readl(xhci_regs + offset);
++ reg &= ~PORT_POWER;
++ writel(reg, xhci_regs + offset);
++ }
++
++ iounmap(xhci_regs);
++ } else
++ dev_err(dwc->dev, "xhci base reg invalid\n");
++}
++
+ static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
+ {
+ u32 reg;
+@@ -111,6 +146,15 @@ static void dwc3_set_prtcap(struct dwc3
+ reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
+ reg |= DWC3_GCTL_PRTCAPDIR(mode);
+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
++
++ /*
++ * We have to power off all Root hub ports immediately after DWC3 set
++ * to host mode to avoid VBUS glitch happen when xhci get reset later.
++ */
++ if (dwc->host_vbus_glitches) {
++ if (mode == DWC3_GCTL_PRTCAP_HOST)
++ dwc3_power_off_all_roothub_ports(dwc);
++ }
+ }
+
+ static void __dwc3_set_mode(struct work_struct *work)
+@@ -765,6 +809,96 @@ static void dwc3_core_setup_global_contr