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ramips: unielec-u7621-01: Increase SPI frequency to 50MHz
[openwrt/openwrt.git]
/
target
/
linux
/
ramips
/
dts
/
mt7628an.dtsi
diff --git
a/target/linux/ramips/dts/mt7628an.dtsi
b/target/linux/ramips/dts/mt7628an.dtsi
index 5998a1187b1183dc471f5cfa89544fb98fc2173c..97f77f6b38b82b70626ddcc790cf3d5c3c467a0c 100644
(file)
--- a/
target/linux/ramips/dts/mt7628an.dtsi
+++ b/
target/linux/ramips/dts/mt7628an.dtsi
@@
-1,7
+1,13
@@
+/dts-v1/;
+
/ {
#address-cells = <1>;
#size-cells = <1>;
/ {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "ralink,mtk7628an-soc";
+ compatible = "mediatek,mt7628an-soc";
+
+ aliases {
+ serial0 = &uartlite;
+ };
cpus {
#address-cells = <1>;
cpus {
#address-cells = <1>;
@@
-17,11
+23,7
@@
bootargs = "console=ttyS0,57600";
};
bootargs = "console=ttyS0,57600";
};
- aliases {
- serial0 = &uartlite;
- };
-
- cpuintc: cpuintc@0 {
+ cpuintc: cpuintc {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
@@
-36,29
+38,23
@@
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
- sysc: sysc@0 {
- compatible = "ralink,mt762
0a
-sysc", "syscon";
+ sysc: sysc
on
@0 {
+ compatible = "ralink,mt762
8
-sysc", "syscon";
reg = <0x0 0x100>;
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
watchdog: watchdog@100 {
};
watchdog: watchdog@100 {
- compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt";
- reg = <0x100 0x30>;
-
- resets = <&rstctrl 8>;
- reset-names = "wdt";
-
- interrupt-parent = <&intc>;
- interrupts = <24>;
+ compatible = "mediatek,mt7621-wdt";
+ reg = <0x100 0x100>;
+ mediatek,sysctl = <&sysc>;
};
intc: intc@200 {
compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
};
intc: intc@200 {
compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
reg = <0x200 0x100>;
- resets = <&rstctrl 9>;
- reset-names = "intc";
-
interrupt-controller;
#interrupt-cells = <1>;
interrupt-controller;
#interrupt-cells = <1>;
@@
-74,50
+70,32
@@
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
- reset-names = "mc";
-
interrupt-parent = <&intc>;
interrupts = <3>;
};
interrupt-parent = <&intc>;
interrupts = <3>;
};
- gpio@600 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
+ gpio: gpio@600 {
+ compatible = "mediatek,mt7621-gpio";
reg = <0x600 0x100>;
interrupt-parent = <&intc>;
interrupts = <6>;
reg = <0x600 0x100>;
interrupt-parent = <&intc>;
interrupts = <6>;
- gpio0: bank@0 {
- reg = <0>;
- compatible = "mtk,mt7621-gpio-bank";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio1: bank@1 {
- reg = <1>;
- compatible = "mtk,mt7621-gpio-bank";
- gpio-controller;
- #gpio-cells = <2>;
- };
+ #interrupt-cells = <2>;
+ interrupt-controller;
- gpio2: bank@2 {
- reg = <2>;
- compatible = "mtk,mt7621-gpio-bank";
- gpio-controller;
- #gpio-cells = <2>;
- };
+ gpio-controller;
+ #gpio-cells = <2>;
};
i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
};
i2c: i2c@900 {
compatible = "mediatek,mt7621-i2c";
reg = <0x900 0x100>;
- resets = <&rstctrl 16>;
+ clocks = <&sysc 7>;
+ clock-names = "i2c";
+
+ resets = <&sysc 16>;
reset-names = "i2c";
#address-cells = <1>;
reset-names = "i2c";
#address-cells = <1>;
@@
-133,7
+111,9
@@
compatible = "mediatek,mt7628-i2s";
reg = <0xa00 0x100>;
compatible = "mediatek,mt7628-i2s";
reg = <0xa00 0x100>;
- resets = <&rstctrl 17>;
+ clocks = <&sysc 8>;
+
+ resets = <&sysc 17>;
reset-names = "i2s";
interrupt-parent = <&intc>;
reset-names = "i2s";
interrupt-parent = <&intc>;
@@
-153,7
+133,10
@@
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>;
- resets = <&rstctrl 18>;
+ clocks = <&sysc 9>;
+ clock-names = "spi";
+
+ resets = <&sysc 18>;
reset-names = "spi";
#address-cells = <1>;
reset-names = "spi";
#address-cells = <1>;
@@
-165,7
+148,7
@@
status = "disabled";
};
status = "disabled";
};
- uartlite: uart
lite
@c00 {
+ uartlite: uart
0
@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
compatible = "ns16550a";
reg = <0xc00 0x100>;
@@
-173,10
+156,9
@@
reg-io-width = <4>;
no-loopback-test;
reg-io-width = <4>;
no-loopback-test;
- clock
-frequency = <40000000
>;
+ clock
s = <&sysc 11
>;
- resets = <&rstctrl 12>;
- reset-names = "uartl";
+ resets = <&sysc 12>;
interrupt-parent = <&intc>;
interrupts = <20>;
interrupt-parent = <&intc>;
interrupts = <20>;
@@
-193,10
+175,9
@@
reg-io-width = <4>;
no-loopback-test;
reg-io-width = <4>;
no-loopback-test;
- clock
-frequency = <40000000
>;
+ clock
s = <&sysc 12
>;
- resets = <&rstctrl 19>;
- reset-names = "uart1";
+ resets = <&sysc 19>;
interrupt-parent = <&intc>;
interrupts = <21>;
interrupt-parent = <&intc>;
interrupts = <21>;
@@
-215,10
+196,9
@@
reg-io-width = <4>;
no-loopback-test;
reg-io-width = <4>;
no-loopback-test;
- clock
-frequency = <40000000
>;
+ clock
s = <&sysc 13
>;
- resets = <&rstctrl 20>;
- reset-names = "uart2";
+ resets = <&sysc 20>;
interrupt-parent = <&intc>;
interrupts = <22>;
interrupt-parent = <&intc>;
interrupts = <22>;
@@
-232,9
+212,7
@@
pwm: pwm@5000 {
compatible = "mediatek,mt7628-pwm";
reg = <0x5000 0x1000>;
pwm: pwm@5000 {
compatible = "mediatek,mt7628-pwm";
reg = <0x5000 0x1000>;
-
- resets = <&rstctrl 31>;
- reset-names = "pwm";
+ #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
@@
-246,7
+224,7
@@
compatible = "ralink,mt7620a-pcm";
reg = <0x2000 0x800>;
compatible = "ralink,mt7620a-pcm";
reg = <0x2000 0x800>;
- resets = <&
rstctrl
11>;
+ resets = <&
sysc
11>;
reset-names = "pcm";
interrupt-parent = <&intc>;
reset-names = "pcm";
interrupt-parent = <&intc>;
@@
-259,7
+237,7
@@
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
- resets = <&
rstctrl
14>;
+ resets = <&
sysc
14>;
reset-names = "dma";
interrupt-parent = <&intc>;
reset-names = "dma";
interrupt-parent = <&intc>;
@@
-281,111
+259,100
@@
state_default: pinctrl0 {
};
state_default: pinctrl0 {
};
- spi_pins: spi {
- spi {
-
ralink,group
= "spi";
-
ralink,
function = "spi";
+ spi_pins: spi
_pins
{
+ spi
_pins
{
+
groups
= "spi";
+ function = "spi";
};
};
spi_cs1_pins: spi_cs1 {
spi_cs1 {
};
};
spi_cs1_pins: spi_cs1 {
spi_cs1 {
-
ralink,group
= "spi cs1";
-
ralink,
function = "spi cs1";
+
groups
= "spi cs1";
+ function = "spi cs1";
};
};
};
};
- i2c_pins: i2c {
- i2c {
-
ralink,group
= "i2c";
-
ralink,
function = "i2c";
+ i2c_pins: i2c
_pins
{
+ i2c
_pins
{
+
groups
= "i2c";
+ function = "i2c";
};
};
i2s_pins: i2s {
i2s {
};
};
i2s_pins: i2s {
i2s {
-
ralink,group
= "i2s";
-
ralink,
function = "i2s";
+
groups
= "i2s";
+ function = "i2s";
};
};
uart0_pins: uartlite {
uartlite {
};
};
uart0_pins: uartlite {
uartlite {
-
ralink,group
= "uart0";
-
ralink,
function = "uart0";
+
groups
= "uart0";
+ function = "uart0";
};
};
uart1_pins: uart1 {
uart1 {
};
};
uart1_pins: uart1 {
uart1 {
-
ralink,group
= "uart1";
-
ralink,
function = "uart1";
+
groups
= "uart1";
+ function = "uart1";
};
};
uart2_pins: uart2 {
uart2 {
};
};
uart2_pins: uart2 {
uart2 {
-
ralink,group
= "uart2";
-
ralink,
function = "uart2";
+
groups
= "uart2";
+ function = "uart2";
};
};
sdxc_pins: sdxc {
sdxc {
};
};
sdxc_pins: sdxc {
sdxc {
-
ralink,group
= "sdmode";
-
ralink,
function = "sdxc";
+
groups
= "sdmode";
+ function = "sdxc";
};
};
pwm0_pins: pwm0 {
pwm0 {
};
};
pwm0_pins: pwm0 {
pwm0 {
-
ralink,group
= "pwm0";
-
ralink,
function = "pwm0";
+
groups
= "pwm0";
+ function = "pwm0";
};
};
pwm1_pins: pwm1 {
pwm1 {
};
};
pwm1_pins: pwm1 {
pwm1 {
-
ralink,group
= "pwm1";
-
ralink,
function = "pwm1";
+
groups
= "pwm1";
+ function = "pwm1";
};
};
pcm_i2s_pins: pcm_i2s {
pcm_i2s {
};
};
pcm_i2s_pins: pcm_i2s {
pcm_i2s {
-
ralink,group
= "i2s";
-
ralink,
function = "pcm";
+
groups
= "i2s";
+ function = "pcm";
};
};
refclk_pins: refclk {
refclk {
};
};
refclk_pins: refclk {
refclk {
-
ralink,group
= "refclk";
-
ralink,
function = "refclk";
+
groups
= "refclk";
+ function = "refclk";
};
};
};
};
};
};
- rstctrl: rstctrl {
- compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
- #reset-cells = <1>;
- };
-
- clkctrl: clkctrl {
- compatible = "ralink,rt2880-clock";
- #clock-cells = <1>;
- };
-
usbphy: usbphy@10120000 {
compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
reg = <0x10120000 0x1000>;
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
usbphy: usbphy@10120000 {
compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
reg = <0x10120000 0x1000>;
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
- resets = <&rstctrl 22 &rstctrl 25>;
+ /* usb phy reset is only controled by RSTCTRL bit 22 */
+ resets = <&sysc 22>, <&sysc 25>;
reset-names = "host", "device";
reset-names = "host", "device";
- clocks = <&clkctrl 22 &clkctrl 25>;
- clock-names = "host", "device";
};
sdhci: sdhci@10130000 {
};
sdhci: sdhci@10130000 {
@@
-402,6
+369,8
@@
};
ehci: ehci@101c0000 {
};
ehci: ehci@101c0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "generic-ehci";
reg = <0x101c0000 0x1000>;
compatible = "generic-ehci";
reg = <0x101c0000 0x1000>;
@@
-410,9
+379,16
@@
interrupt-parent = <&intc>;
interrupts = <18>;
interrupt-parent = <&intc>;
interrupts = <18>;
+
+ ehci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
};
ohci: ohci@101c1000 {
};
ohci: ohci@101c1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "generic-ohci";
reg = <0x101c1000 0x1000>;
compatible = "generic-ohci";
reg = <0x101c1000 0x1000>;
@@
-421,6
+397,11
@@
interrupt-parent = <&intc>;
interrupts = <18>;
interrupt-parent = <&intc>;
interrupts = <18>;
+
+ ohci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
};
ethernet: ethernet@10100000 {
};
ethernet: ethernet@10100000 {
@@
-430,7
+411,7
@@
interrupt-parent = <&cpuintc>;
interrupts = <5>;
interrupt-parent = <&cpuintc>;
interrupts = <5>;
- resets = <&
rstctrl 21 &rstctrl
23>;
+ resets = <&
sysc 21>, <&sysc
23>;
reset-names = "fe", "esw";
mediatek,switch = <&esw>;
reset-names = "fe", "esw";
mediatek,switch = <&esw>;
@@
-440,8
+421,8
@@
compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
reg = <0x10110000 0x8000>;
- resets = <&
rstctrl 23
>;
- reset-names = "e
sw
";
+ resets = <&
sysc 24
>;
+ reset-names = "e
phy
";
interrupt-parent = <&intc>;
interrupts = <17>;
interrupt-parent = <&intc>;
interrupts = <17>;
@@
-458,10
+439,8
@@
interrupt-parent = <&cpuintc>;
interrupts = <4>;
interrupt-parent = <&cpuintc>;
interrupts = <4>;
- resets = <&rstctrl 26 &rstctrl 27>;
- reset-names = "pcie0", "pcie1";
- clocks = <&clkctrl 26 &clkctrl 27>;
- clock-names = "pcie0", "pcie1";
+ resets = <&sysc 26>;
+ reset-names = "pcie0";
status = "disabled";
status = "disabled";
@@
-473,13
+452,15
@@
0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
>;
0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
>;
- pcie
-bridge
{
+ pcie
0: pcie@0,0
{
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+
+ ranges;
};
};
};
};
@@
-487,11
+468,11
@@
compatible = "mediatek,mt7628-wmac";
reg = <0x10300000 0x100000>;
compatible = "mediatek,mt7628-wmac";
reg = <0x10300000 0x100000>;
+ clocks = <&sysc 14>;
+
interrupt-parent = <&cpuintc>;
interrupts = <6>;
status = "disabled";
interrupt-parent = <&cpuintc>;
interrupts = <6>;
status = "disabled";
-
- mediatek,mtd-eeprom = <&factory 0x0000>;
};
};
};
};