case ATH79_SOC_AR7241:
case ATH79_SOC_AR9330:
case ATH79_SOC_AR9331:
- case ATH79_SOC_QCA956X:
case ATH79_SOC_TP9343:
pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
break;
case ATH79_SOC_AR9342:
case ATH79_SOC_AR9344:
case ATH79_SOC_QCA9533:
+ case ATH79_SOC_QCA956X:
switch (pdata->phy_if_mode) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_GMII:
iounmap(base);
}
+void __init ath79_setup_qca956x_eth_cfg(u32 mask)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA956X_GMAC_BASE, QCA956X_GMAC_SIZE);
+
+ t = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
+
+ t &= ~(QCA956X_ETH_CFG_SW_ONLY_MODE |
+ QCA956X_ETH_CFG_SW_PHY_SWAP);
+
+ t |= mask;
+
+ __raw_writel(t, base + QCA956X_GMAC_REG_ETH_CFG);
+ /* flush write */
+ __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
static int ath79_eth_instance __initdata;
void __init ath79_register_eth(unsigned int id)
{
if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
pdata->set_speed = qca956x_set_speed_sgmii;
else
- pdata->set_speed = ath79_set_speed_ge0;
+ pdata->set_speed = ar934x_set_speed_ge0;
} else {
pdata->reset_bit = QCA955X_RESET_GE1_MAC |
QCA955X_RESET_GE1_MDIO;