ar71xx: register the second ethernet interface on the AP136

[openwrt/openwrt.git] / target / linux / ar71xx / patches-3.6 / 609-MIPS-ath79-ap136-fixes.patch

diff --git a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
index bd07c7bc828f79bdf9985f3c24b8a0ee5c0cfa5a..58cd680ce41f20d4110cd0400882ccff80551dc2 100644 (file)
--- a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
+++ b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
@@ -56,7 +56,7 @@
  
  static struct gpio_led ap136_leds_gpio[] __initdata = {
        {
-@@ -98,63 +104,82 @@ static struct gpio_keys_button ap136_gpi
+@@ -98,63 +104,106 @@ static struct gpio_keys_button ap136_gpi
        },
  };
  
@@ -78,31 +78,47 @@
 -              .max_speed_hz   = 25000000,
 -              .modalias       = "mx25l6405d",
 -              .controller_data = &ap136_spi0_data,
+-      }
++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg = {
++      .mode = AR8327_PAD_MAC_SGMII,
++      .txclk_delay_en = false,
++      .rxclk_delay_en = true,
++      .txclk_delay_sel = AR8327_CLK_DELAY_SEL0,
++      .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
+ };
+ 
+-static struct ath79_spi_platform_data ap136_spi_data = {
+-      .bus_num        = 0,
+-      .num_chipselect = 1,
 +static struct ar8327_platform_data ap136_ar8327_data = {
 +      .pad0_cfg = &ap136_ar8327_pad0_cfg,
-+      .cpuport_cfg = {
++      .pad6_cfg = &ap136_ar8327_pad6_cfg,
++      .port0_cfg = {
++              .force_link = 1,
++              .speed = AR8327_PORT_SPEED_1000,
++              .duplex = 1,
++              .txpause = 1,
++              .rxpause = 1,
++      },
++      .port6_cfg = {
 +              .force_link = 1,
 +              .speed = AR8327_PORT_SPEED_1000,
 +              .duplex = 1,
 +              .txpause = 1,
 +              .rxpause = 1,
-       }
++      },
  };
  
--static struct ath79_spi_platform_data ap136_spi_data = {
--      .bus_num        = 0,
--      .num_chipselect = 1,
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ap136_ath9k_data;
 +static struct mdio_board_info ap136_mdio0_info[] = {
 +      {
 +              .bus_id = "ag71xx-mdio.0",
 +              .phy_addr = 0,
 +              .platform_data = &ap136_ar8327_data,
 +      },
- };
++};
  
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data ap136_ath9k_data;
--
 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
 +static void __init ap136_gmac_setup(void)
  {
@@ -121,13 +137,13 @@
 -             sizeof(ap136_ath9k_data.eeprom_data));
 +      t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 +
-+      t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
-+      t |= QCA955X_ETH_CFG_RGMII_GMAC0;
++      t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
++      t |= QCA955X_ETH_CFG_RGMII_EN;
++
++      __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
  
 -      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
 -      ath79_register_pci();
-+      __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
-+
 +      iounmap(base);
  }
 -#else
@@ -163,13 +179,21 @@
 +      mdiobus_register_board_info(ap136_mdio0_info,
 +                                  ARRAY_SIZE(ap136_mdio0_info));
 +
-+      /* GMAC0 is connected to an AR8327 switch */
++      /* GMAC0 is connected to GMAC0 of the AR8327 switch via RGMII */
 +      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 +      ath79_eth0_data.phy_mask = BIT(0);
 +      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
-+      ath79_eth0_pll_data.pll_1000 = 0x06000000;
++      ath79_eth0_pll_data.pll_1000 = 0xa6000000;
 +
 +      ath79_register_eth(0);
++
++      /* GMAC1 is connected to GMAC6 of the AR8327 switch via SGMII */
++      ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
++      ath79_eth1_data.speed = SPEED_1000;
++      ath79_eth1_data.duplex = DUPLEX_FULL;
++      ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++      ath79_register_eth(1);
  }
  
  MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",