ath79: add missing clock name strings in SoC dtsi

[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9563_elecom_wrc-300ghbk2-i.dts

diff --git a/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts b/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
index 778e0fd52ec19b9bf690b38696d0b4ad45d1a933..5ffff57b48231348bf7cf0918f463b369d09379f 100644 (file)
--- a/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
+++ b/target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts
@@ -1,8 +1,4 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
 
 #include "qca9563_elecom_wrc-ghbk2-i.dtsi"
 
@@ -12,14 +8,14 @@
 };
 
 &leds {
-       power: power {
-               label = "elecom:white:power";
+       led_power: power {
+               label = "white:power";
                gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
                default-state = "on";
        };
 
        wlan2g {
-               label = "elecom:white:wlan2g";
+               label = "white:wlan2g";
                gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
                linux,default-trigger = "phy0tpt";
        };
@@ -42,5 +38,28 @@
                label = "art";
                reg = <0x7f0000 0x010000>;
                read-only;
+
+               compatible = "nvmem-cells";
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               cal_art_1000: cal@1000 {
+                       reg = <0x1000 0x440>;
+               };
+
+               macaddr_art_1002: macaddr@1002 {
+                       reg = <0x1002 0x6>;
+               };
        };
 };
+
+&eth0 {
+       nvmem-cells = <&macaddr_art_1002>;
+       nvmem-cell-names = "mac-address";
+       mac-address-increment = <(-1)>;
+};
+
+&wmac {
+       nvmem-cells = <&cal_art_1000>;
+       nvmem-cell-names = "calibration";
+};