ath79: enable UART in SoC DTSI files

[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9563_tplink_tl-wpa8630.dtsi

diff --git a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi
index 14602a1c24393f13255b6662e9a85be1cd1064c2..5fd314b85608767611702e44b0972f5d9af96567 100644 (file)
--- a/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi
+++ b/target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi
@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include "qca956x.dtsi"
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
-#include "qca956x.dtsi"
-
 / {
        aliases {
                led-boot = &led_power;
@@ -49,23 +49,23 @@
                compatible = "gpio-leds";
 
                led_power: power {
-                       label = "tp-link:green:power";
+                       label = "green:power";
                        gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
                };
 
                lan {
-                       label = "tp-link:green:lan";
+                       label = "green:lan";
                        gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
                };
 
                wifi2g {
-                       label = "tp-link:green:wifi2g";
+                       label = "green:wifi2g";
                        gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "phy1tpt";
                };
 
                wifi5g {
-                       label = "tp-link:green:wifi5g";
+                       label = "green:wifi5g";
                        gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
                        linux,default-trigger = "phy0tpt";
                };
@@ -85,8 +85,6 @@
 &spi {
        status = "okay";
 
-       num-cs = <1>;
-
        flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0>;
@@ -104,10 +102,6 @@
        status = "okay";
 };
 
-&uart {
-       status = "okay";
-};
-
 &mdio0 {
        status = "okay";