--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
-@@ -467,11 +467,13 @@ static int vc4_plane_mode_set(struct drm
+@@ -469,11 +469,13 @@ static int vc4_plane_mode_set(struct drm
struct drm_framebuffer *fb = state->fb;
u32 ctl0_offset = vc4_state->dlist_count;
const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
int ret, i;
ret = vc4_plane_setup_clipping_and_scaling(state);
-@@ -511,7 +513,7 @@ static int vc4_plane_mode_set(struct drm
+@@ -513,7 +515,7 @@ static int vc4_plane_mode_set(struct drm
scl1 = vc4_get_scl_field(state, 0);
}
case DRM_FORMAT_MOD_LINEAR:
tiling = SCALER_CTL0_TILING_LINEAR;
pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
-@@ -534,6 +536,49 @@ static int vc4_plane_mode_set(struct drm
+@@ -536,6 +538,49 @@ static int vc4_plane_mode_set(struct drm
break;
}
default:
DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
(long long)fb->modifier);
-@@ -544,7 +589,7 @@ static int vc4_plane_mode_set(struct drm
+@@ -546,7 +591,7 @@ static int vc4_plane_mode_set(struct drm
vc4_dlist_write(vc4_state,
SCALER_CTL0_VALID |
(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
-@@ -598,8 +643,13 @@ static int vc4_plane_mode_set(struct drm
+@@ -600,8 +645,13 @@ static int vc4_plane_mode_set(struct drm
/* Pitch word 1/2 */
for (i = 1; i < num_planes; i++) {
}
/* Colorspace conversion words */
-@@ -882,13 +932,30 @@ static bool vc4_format_mod_supported(str
+@@ -884,13 +934,30 @@ static bool vc4_format_mod_supported(str
case DRM_FORMAT_BGR565:
case DRM_FORMAT_ARGB1555:
case DRM_FORMAT_XRGB1555:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
default:
-@@ -918,6 +985,9 @@ struct drm_plane *vc4_plane_init(struct
+@@ -920,6 +987,9 @@ struct drm_plane *vc4_plane_init(struct
unsigned i;
static const uint64_t modifiers[] = {
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,