--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
-@@ -25,6 +25,38 @@
+@@ -26,6 +26,38 @@
extern void (*r4k_blast_dcache)(void);
extern void (*r4k_blast_icache)(void);
/*
* This macro return a properly sign-extended address suitable as base address
* for indexed cache operations. Two issues here:
-@@ -98,6 +130,7 @@ static inline void flush_icache_line_ind
+@@ -99,6 +131,7 @@ static inline void flush_icache_line_ind
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__dflush_prologue
cache_op(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -125,6 +158,7 @@ static inline void flush_icache_line(uns
+@@ -126,6 +159,7 @@ static inline void flush_icache_line(uns
static inline void flush_dcache_line(unsigned long addr)
{
__dflush_prologue
cache_op(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
-@@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns
+@@ -133,6 +167,7 @@ static inline void flush_dcache_line(uns
static inline void invalidate_dcache_line(unsigned long addr)
{
__dflush_prologue
cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
-@@ -205,6 +240,7 @@ static inline int protected_flush_icache
+@@ -206,6 +241,7 @@ static inline int protected_flush_icache
#ifdef CONFIG_EVA
return protected_cachee_op(Hit_Invalidate_I, addr);
#else
return protected_cache_op(Hit_Invalidate_I, addr);
#endif
}
-@@ -218,6 +254,7 @@ static inline int protected_flush_icache
+@@ -219,6 +255,7 @@ static inline int protected_flush_icache
*/
static inline int protected_writeback_dcache_line(unsigned long addr)
{
#ifdef CONFIG_EVA
return protected_cachee_op(Hit_Writeback_Inv_D, addr);
#else
-@@ -575,8 +612,51 @@ static inline void invalidate_tcache_pag
+@@ -576,8 +613,51 @@ static inline void invalidate_tcache_pag
: "r" (base), \
"i" (op));
static inline void extra##blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
-@@ -588,6 +668,7 @@ static inline void extra##blast_##pfx##c
+@@ -589,6 +669,7 @@ static inline void extra##blast_##pfx##c
\
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws, indexop); \
-@@ -602,6 +683,7 @@ static inline void extra##blast_##pfx##c
+@@ -603,6 +684,7 @@ static inline void extra##blast_##pfx##c
\
__##pfx##flush_prologue \
\
do { \
cache##lsize##_unroll32(start, hitop); \
start += lsize * 32; \
-@@ -620,6 +702,8 @@ static inline void extra##blast_##pfx##c
+@@ -621,6 +703,8 @@ static inline void extra##blast_##pfx##c
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
-@@ -629,26 +713,26 @@ static inline void extra##blast_##pfx##c
+@@ -630,26 +714,26 @@ static inline void extra##blast_##pfx##c
__##pfx##flush_epilogue \
}
#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
-@@ -677,53 +761,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
+@@ -678,53 +762,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
/* build blast_xxx_range, protected_blast_xxx_range */
} \
\
__##pfx##flush_epilogue \
-@@ -731,8 +785,8 @@ static inline void prot##extra##blast_##
+@@ -732,8 +786,8 @@ static inline void prot##extra##blast_##
#ifndef CONFIG_EVA
#else
-@@ -769,14 +823,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
+@@ -770,15 +824,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
#endif
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
- #endif /* _ASM_R4KCACHE_H */
+ /* Currently, this is very specific to Loongson-3 */
+ #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -428,6 +428,10 @@
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -952,6 +964,8 @@ static void local_r4k_flush_cache_sigtra
+@@ -986,6 +998,8 @@ static void local_r4k_flush_cache_sigtra
}
R4600_HIT_CACHEOP_WAR_IMPL;
if (!cpu_has_ic_fills_f_dc) {
if (dc_lsize)
vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
-@@ -1846,6 +1860,17 @@ static void coherency_setup(void)
+@@ -1880,6 +1894,17 @@ static void coherency_setup(void)
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1892,6 +1917,15 @@ void r4k_cache_init(void)
+@@ -1926,6 +1951,15 @@ void r4k_cache_init(void)
extern void build_copy_page(void);
struct cpuinfo_mips *c = ¤t_cpu_data;
probe_pcache();
probe_vcache();
setup_scache();
-@@ -1969,7 +2003,15 @@ void r4k_cache_init(void)
+@@ -2004,7 +2038,15 @@ void r4k_cache_init(void)
*/
local_r4k___flush_cache_all(NULL);
/*
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
-@@ -971,6 +971,9 @@ void build_get_pgde32(u32 **p, unsigned
+@@ -983,6 +983,9 @@ void build_get_pgde32(u32 **p, unsigned
uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
uasm_i_addu(p, ptr, tmp, ptr);
#else
UASM_i_LA_mostly(p, ptr, pgdc);
#endif
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-@@ -1331,6 +1334,9 @@ static void build_r4000_tlb_refill_handl
+@@ -1344,6 +1347,9 @@ static void build_r4000_tlb_refill_handl
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
#endif
-@@ -1342,6 +1348,9 @@ static void build_r4000_tlb_refill_handl
+@@ -1355,6 +1361,9 @@ static void build_r4000_tlb_refill_handl
build_update_entries(&p, K0, K1);
build_tlb_write_entry(&p, &l, &r, tlb_random);
uasm_l_leave(&l, p);
uasm_i_eret(&p); /* return from trap */
}
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-@@ -2046,6 +2055,9 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -2064,6 +2073,9 @@ build_r4000_tlbchange_handler_head(u32 *
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
#else
build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
#endif
-@@ -2092,6 +2104,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+@@ -2110,6 +2122,9 @@ build_r4000_tlbchange_handler_tail(u32 *
build_tlb_write_entry(p, l, r, tlb_indexed);
uasm_l_leave(l, *p);
build_restore_work_registers(p);