if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -955,6 +967,8 @@ static void local_r4k_flush_cache_sigtra
+@@ -957,6 +969,8 @@ static void local_r4k_flush_cache_sigtra
}
R4600_HIT_CACHEOP_WAR_IMPL;
if (!cpu_has_ic_fills_f_dc) {
if (dc_lsize)
vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
-@@ -1843,6 +1857,17 @@ static void coherency_setup(void)
+@@ -1845,6 +1859,17 @@ static void coherency_setup(void)
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1889,6 +1914,15 @@ void r4k_cache_init(void)
+@@ -1891,6 +1916,15 @@ void r4k_cache_init(void)
extern void build_copy_page(void);
struct cpuinfo_mips *c = ¤t_cpu_data;
probe_pcache();
probe_vcache();
setup_scache();
-@@ -1966,7 +2000,15 @@ void r4k_cache_init(void)
+@@ -1968,7 +2002,15 @@ void r4k_cache_init(void)
*/
local_r4k___flush_cache_all(NULL);