/* strings used by ethtool */
static const struct mtk_ethtool_stats {
char str[ETH_GSTRING_LEN];
-@@ -618,8 +671,8 @@ static inline void mtk_tx_irq_disable(st
+@@ -619,8 +672,8 @@ static inline void mtk_tx_irq_disable(st
u32 val;
spin_lock_irqsave(ð->tx_irq_lock, flags);
spin_unlock_irqrestore(ð->tx_irq_lock, flags);
}
-@@ -629,8 +682,8 @@ static inline void mtk_tx_irq_enable(str
+@@ -630,8 +683,8 @@ static inline void mtk_tx_irq_enable(str
u32 val;
spin_lock_irqsave(ð->tx_irq_lock, flags);
spin_unlock_irqrestore(ð->tx_irq_lock, flags);
}
-@@ -640,8 +693,8 @@ static inline void mtk_rx_irq_disable(st
+@@ -641,8 +694,8 @@ static inline void mtk_rx_irq_disable(st
u32 val;
spin_lock_irqsave(ð->rx_irq_lock, flags);
spin_unlock_irqrestore(ð->rx_irq_lock, flags);
}
-@@ -651,8 +704,8 @@ static inline void mtk_rx_irq_enable(str
+@@ -652,8 +705,8 @@ static inline void mtk_rx_irq_enable(str
u32 val;
spin_lock_irqsave(ð->rx_irq_lock, flags);
spin_unlock_irqrestore(ð->rx_irq_lock, flags);
}
-@@ -703,39 +756,39 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -704,39 +757,39 @@ void mtk_stats_update_mac(struct mtk_mac
hw_stats->rx_checksum_errors +=
mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
} else {
}
u64_stats_update_end(&hw_stats->syncp);
-@@ -864,10 +917,10 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -876,10 +929,10 @@ static int mtk_init_fq_dma(struct mtk_et
txd->txd4 = 0;
}
return 0;
}
-@@ -1111,7 +1164,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1123,7 +1176,7 @@ static int mtk_tx_map(struct sk_buff *sk
if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
!netdev_xmit_more())
} else {
int next_idx;
-@@ -1425,6 +1478,7 @@ rx_done:
+@@ -1440,6 +1493,7 @@ rx_done:
static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
unsigned int *done, unsigned int *bytes)
{
struct mtk_tx_ring *ring = ð->tx_ring;
struct mtk_tx_dma *desc;
struct sk_buff *skb;
-@@ -1432,7 +1486,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -1447,7 +1501,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
u32 cpu, dma;
cpu = ring->last_free_ptr;
desc = mtk_qdma_phys_to_virt(ring, cpu);
-@@ -1467,7 +1521,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -1482,7 +1536,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
}
ring->last_free_ptr = cpu;
return budget;
}
-@@ -1560,24 +1614,25 @@ static void mtk_handle_status_irq(struct
+@@ -1575,24 +1629,25 @@ static void mtk_handle_status_irq(struct
static int mtk_napi_tx(struct napi_struct *napi, int budget)
{
struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
return budget;
if (napi_complete_done(napi, tx_done))
-@@ -1589,6 +1644,7 @@ static int mtk_napi_tx(struct napi_struc
+@@ -1604,6 +1659,7 @@ static int mtk_napi_tx(struct napi_struc
static int mtk_napi_rx(struct napi_struct *napi, int budget)
{
struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
int rx_done_total = 0;
mtk_handle_status_irq(eth);
-@@ -1596,21 +1652,21 @@ static int mtk_napi_rx(struct napi_struc
+@@ -1611,21 +1667,21 @@ static int mtk_napi_rx(struct napi_struc
do {
int rx_done;
if (napi_complete_done(napi, rx_done_total))
mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
-@@ -1673,20 +1729,20 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -1688,20 +1744,20 @@ static int mtk_tx_alloc(struct mtk_eth *
*/
wmb();
}
return 0;
-@@ -1725,6 +1781,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -1740,6 +1796,7 @@ static void mtk_tx_clean(struct mtk_eth
static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
{
struct mtk_rx_ring *ring;
int rx_data_len, rx_dma_size;
int i;
-@@ -1790,16 +1847,18 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -1808,16 +1865,18 @@ static int mtk_rx_alloc(struct mtk_eth *
ring->dma_size = rx_dma_size;
ring->calc_idx_update = false;
ring->calc_idx = rx_dma_size - 1;
return 0;
}
-@@ -2105,9 +2164,9 @@ static int mtk_dma_busy_wait(struct mtk_
+@@ -2129,9 +2188,9 @@ static int mtk_dma_busy_wait(struct mtk_
u32 val;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
!(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
-@@ -2165,8 +2224,8 @@ static int mtk_dma_init(struct mtk_eth *
+@@ -2189,8 +2248,8 @@ static int mtk_dma_init(struct mtk_eth *
* automatically
*/
mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
}
return 0;
-@@ -2240,13 +2299,14 @@ static irqreturn_t mtk_handle_irq_tx(int
+@@ -2264,13 +2323,14 @@ static irqreturn_t mtk_handle_irq_tx(int
static irqreturn_t mtk_handle_irq(int irq, void *_eth)
{
struct mtk_eth *eth = _eth;
mtk_handle_irq_tx(irq, _eth);
}
-@@ -2270,6 +2330,7 @@ static void mtk_poll_controller(struct n
+@@ -2294,6 +2354,7 @@ static void mtk_poll_controller(struct n
static int mtk_start_dma(struct mtk_eth *eth)
{
u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
int err;
err = mtk_dma_init(eth);
-@@ -2284,16 +2345,15 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2308,16 +2369,15 @@ static int mtk_start_dma(struct mtk_eth
MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
MTK_RX_BT_32DWORDS,
}
return 0;
-@@ -2417,8 +2477,8 @@ static int mtk_stop(struct net_device *d
+@@ -2443,8 +2503,8 @@ static int mtk_stop(struct net_device *d
cancel_work_sync(ð->tx_dim.work);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
mtk_dma_free(eth);
-@@ -2472,6 +2532,7 @@ static void mtk_dim_rx(struct work_struc
+@@ -2498,6 +2558,7 @@ static void mtk_dim_rx(struct work_struc
{
struct dim *dim = container_of(work, struct dim, work);
struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
struct dim_cq_moder cur_profile;
u32 val, cur;
-@@ -2479,7 +2540,7 @@ static void mtk_dim_rx(struct work_struc
+@@ -2505,7 +2566,7 @@ static void mtk_dim_rx(struct work_struc
dim->profile_ix);
spin_lock_bh(ð->dim_lock);
val &= MTK_PDMA_DELAY_TX_MASK;
val |= MTK_PDMA_DELAY_RX_EN;
-@@ -2489,9 +2550,9 @@ static void mtk_dim_rx(struct work_struc
+@@ -2515,9 +2576,9 @@ static void mtk_dim_rx(struct work_struc
cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
spin_unlock_bh(ð->dim_lock);
-@@ -2502,6 +2563,7 @@ static void mtk_dim_tx(struct work_struc
+@@ -2528,6 +2589,7 @@ static void mtk_dim_tx(struct work_struc
{
struct dim *dim = container_of(work, struct dim, work);
struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
struct dim_cq_moder cur_profile;
u32 val, cur;
-@@ -2509,7 +2571,7 @@ static void mtk_dim_tx(struct work_struc
+@@ -2535,7 +2597,7 @@ static void mtk_dim_tx(struct work_struc
dim->profile_ix);
spin_lock_bh(ð->dim_lock);
val &= MTK_PDMA_DELAY_RX_MASK;
val |= MTK_PDMA_DELAY_TX_EN;
-@@ -2519,9 +2581,9 @@ static void mtk_dim_tx(struct work_struc
+@@ -2545,9 +2607,9 @@ static void mtk_dim_tx(struct work_struc
cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
spin_unlock_bh(ð->dim_lock);
-@@ -2532,6 +2594,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2558,6 +2620,7 @@ static int mtk_hw_init(struct mtk_eth *e
{
u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
ETHSYS_DMA_AG_MAP_PPE;
int i, val, ret;
if (test_and_set_bit(MTK_HW_INIT, ð->state))
-@@ -2606,10 +2669,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2632,10 +2695,10 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_rx_irq_disable(eth, ~0);
/* FE int grouping */
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
return 0;
-@@ -3148,14 +3211,6 @@ static int mtk_probe(struct platform_dev
+@@ -3167,14 +3230,6 @@ static int mtk_probe(struct platform_dev
if (IS_ERR(eth->base))
return PTR_ERR(eth->base);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
eth->ip_align = NET_IP_ALIGN;
-@@ -3389,6 +3444,7 @@ static int mtk_remove(struct platform_de
+@@ -3408,6 +3463,7 @@ static int mtk_remove(struct platform_de
}
static const struct mtk_soc_data mt2701_data = {
.caps = MT7623_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
-@@ -3400,6 +3456,7 @@ static const struct mtk_soc_data mt2701_
+@@ -3419,6 +3475,7 @@ static const struct mtk_soc_data mt2701_
};
static const struct mtk_soc_data mt7621_data = {
.caps = MT7621_CAPS,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7621_CLKS_BITMAP,
-@@ -3412,6 +3469,7 @@ static const struct mtk_soc_data mt7621_
+@@ -3431,6 +3488,7 @@ static const struct mtk_soc_data mt7621_
};
static const struct mtk_soc_data mt7622_data = {
.ana_rgc3 = 0x2028,
.caps = MT7622_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
-@@ -3425,6 +3483,7 @@ static const struct mtk_soc_data mt7622_
+@@ -3444,6 +3502,7 @@ static const struct mtk_soc_data mt7622_
};
static const struct mtk_soc_data mt7623_data = {
.caps = MT7623_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
-@@ -3437,6 +3496,7 @@ static const struct mtk_soc_data mt7623_
+@@ -3456,6 +3515,7 @@ static const struct mtk_soc_data mt7623_
};
static const struct mtk_soc_data mt7629_data = {
.ana_rgc3 = 0x128,
.caps = MT7629_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
-@@ -3449,6 +3509,7 @@ static const struct mtk_soc_data mt7629_
+@@ -3468,6 +3528,7 @@ static const struct mtk_soc_data mt7629_
};
static const struct mtk_soc_data rt5350_data = {
#define MTK_STAT_OFFSET 0x40
#define MTK_WDMA0_BASE 0x2800
-@@ -853,8 +762,46 @@ struct mtk_tx_dma_desc_info {
+@@ -854,8 +763,46 @@ struct mtk_tx_dma_desc_info {
u8 last:1;
};
* @ana_rgc3: The offset for register ANA_RGC3 related to
* sgmiisys syscon
* @caps Flags shown the extra capability for the SoC
-@@ -867,6 +814,7 @@ struct mtk_tx_dma_desc_info {
+@@ -868,6 +815,7 @@ struct mtk_tx_dma_desc_info {
* @rxd_size Rx DMA descriptor size.
*/
struct mtk_soc_data {
u32 ana_rgc3;
u32 caps;
u32 required_clks;
-@@ -994,8 +942,6 @@ struct mtk_eth {
+@@ -995,8 +943,6 @@ struct mtk_eth {
u32 tx_bytes;
struct dim tx_dim;