return 0;
}
-@@ -2105,9 +2164,9 @@ static int mtk_dma_busy_wait(struct mtk_
+@@ -2108,9 +2167,9 @@ static int mtk_dma_busy_wait(struct mtk_
u32 val;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
!(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
-@@ -2165,8 +2224,8 @@ static int mtk_dma_init(struct mtk_eth *
+@@ -2168,8 +2227,8 @@ static int mtk_dma_init(struct mtk_eth *
* automatically
*/
mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
}
return 0;
-@@ -2240,13 +2299,14 @@ static irqreturn_t mtk_handle_irq_tx(int
+@@ -2243,13 +2302,14 @@ static irqreturn_t mtk_handle_irq_tx(int
static irqreturn_t mtk_handle_irq(int irq, void *_eth)
{
struct mtk_eth *eth = _eth;
mtk_handle_irq_tx(irq, _eth);
}
-@@ -2270,6 +2330,7 @@ static void mtk_poll_controller(struct n
+@@ -2273,6 +2333,7 @@ static void mtk_poll_controller(struct n
static int mtk_start_dma(struct mtk_eth *eth)
{
u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
int err;
err = mtk_dma_init(eth);
-@@ -2284,16 +2345,15 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2287,16 +2348,15 @@ static int mtk_start_dma(struct mtk_eth
MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
MTK_RX_BT_32DWORDS,
}
return 0;
-@@ -2417,8 +2477,8 @@ static int mtk_stop(struct net_device *d
+@@ -2420,8 +2480,8 @@ static int mtk_stop(struct net_device *d
cancel_work_sync(ð->tx_dim.work);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
mtk_dma_free(eth);
-@@ -2472,6 +2532,7 @@ static void mtk_dim_rx(struct work_struc
+@@ -2475,6 +2535,7 @@ static void mtk_dim_rx(struct work_struc
{
struct dim *dim = container_of(work, struct dim, work);
struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);
struct dim_cq_moder cur_profile;
u32 val, cur;
-@@ -2479,7 +2540,7 @@ static void mtk_dim_rx(struct work_struc
+@@ -2482,7 +2543,7 @@ static void mtk_dim_rx(struct work_struc
dim->profile_ix);
spin_lock_bh(ð->dim_lock);
val &= MTK_PDMA_DELAY_TX_MASK;
val |= MTK_PDMA_DELAY_RX_EN;
-@@ -2489,9 +2550,9 @@ static void mtk_dim_rx(struct work_struc
+@@ -2492,9 +2553,9 @@ static void mtk_dim_rx(struct work_struc
cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;
spin_unlock_bh(ð->dim_lock);
-@@ -2502,6 +2563,7 @@ static void mtk_dim_tx(struct work_struc
+@@ -2505,6 +2566,7 @@ static void mtk_dim_tx(struct work_struc
{
struct dim *dim = container_of(work, struct dim, work);
struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);
struct dim_cq_moder cur_profile;
u32 val, cur;
-@@ -2509,7 +2571,7 @@ static void mtk_dim_tx(struct work_struc
+@@ -2512,7 +2574,7 @@ static void mtk_dim_tx(struct work_struc
dim->profile_ix);
spin_lock_bh(ð->dim_lock);
val &= MTK_PDMA_DELAY_RX_MASK;
val |= MTK_PDMA_DELAY_TX_EN;
-@@ -2519,9 +2581,9 @@ static void mtk_dim_tx(struct work_struc
+@@ -2522,9 +2584,9 @@ static void mtk_dim_tx(struct work_struc
cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);
val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;
spin_unlock_bh(ð->dim_lock);
-@@ -2532,6 +2594,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2535,6 +2597,7 @@ static int mtk_hw_init(struct mtk_eth *e
{
u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
ETHSYS_DMA_AG_MAP_PPE;
int i, val, ret;
if (test_and_set_bit(MTK_HW_INIT, ð->state))
-@@ -2606,10 +2669,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -2609,10 +2672,10 @@ static int mtk_hw_init(struct mtk_eth *e
mtk_rx_irq_disable(eth, ~0);
/* FE int grouping */
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
return 0;
-@@ -3148,14 +3211,6 @@ static int mtk_probe(struct platform_dev
+@@ -3151,14 +3214,6 @@ static int mtk_probe(struct platform_dev
if (IS_ERR(eth->base))
return PTR_ERR(eth->base);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
eth->ip_align = NET_IP_ALIGN;
-@@ -3389,6 +3444,7 @@ static int mtk_remove(struct platform_de
+@@ -3392,6 +3447,7 @@ static int mtk_remove(struct platform_de
}
static const struct mtk_soc_data mt2701_data = {
.caps = MT7623_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
-@@ -3400,6 +3456,7 @@ static const struct mtk_soc_data mt2701_
+@@ -3403,6 +3459,7 @@ static const struct mtk_soc_data mt2701_
};
static const struct mtk_soc_data mt7621_data = {
.caps = MT7621_CAPS,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7621_CLKS_BITMAP,
-@@ -3412,6 +3469,7 @@ static const struct mtk_soc_data mt7621_
+@@ -3415,6 +3472,7 @@ static const struct mtk_soc_data mt7621_
};
static const struct mtk_soc_data mt7622_data = {
.ana_rgc3 = 0x2028,
.caps = MT7622_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
-@@ -3425,6 +3483,7 @@ static const struct mtk_soc_data mt7622_
+@@ -3428,6 +3486,7 @@ static const struct mtk_soc_data mt7622_
};
static const struct mtk_soc_data mt7623_data = {
.caps = MT7623_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
.required_clks = MT7623_CLKS_BITMAP,
-@@ -3437,6 +3496,7 @@ static const struct mtk_soc_data mt7623_
+@@ -3440,6 +3499,7 @@ static const struct mtk_soc_data mt7623_
};
static const struct mtk_soc_data mt7629_data = {
.ana_rgc3 = 0x128,
.caps = MT7629_CAPS | MTK_HWLRO,
.hw_features = MTK_HW_FEATURES,
-@@ -3449,6 +3509,7 @@ static const struct mtk_soc_data mt7629_
+@@ -3452,6 +3512,7 @@ static const struct mtk_soc_data mt7629_
};
static const struct mtk_soc_data rt5350_data = {