/* Save the syscfg0 value for mac_finish */
mac->syscfg0 = val;
} else if (phylink_autoneg_inband(mode)) {
-@@ -526,14 +536,6 @@ static void mtk_mac_pcs_get_state(struct
+@@ -527,14 +537,6 @@ static void mtk_mac_pcs_get_state(struct
state->pause |= MLO_PAUSE_TX;
}
static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
phy_interface_t interface)
{
-@@ -554,15 +556,6 @@ static void mtk_mac_link_up(struct phyli
+@@ -555,15 +557,6 @@ static void mtk_mac_link_up(struct phyli
phylink_config);
u32 mcr;
mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
-@@ -595,8 +588,8 @@ static void mtk_mac_link_up(struct phyli
+@@ -596,8 +589,8 @@ static void mtk_mac_link_up(struct phyli
static const struct phylink_mac_ops mtk_phylink_ops = {
.validate = phylink_generic_validate,
.mac_link_down = mtk_mac_link_down,
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -963,10 +963,12 @@ struct mtk_soc_data {
+@@ -964,10 +964,12 @@ struct mtk_soc_data {
* @regmap: The register map pointing at the range used to setup
* SGMII modes
* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
};
/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
-@@ -1106,12 +1108,9 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -1107,12 +1109,9 @@ void mtk_stats_update_mac(struct mtk_mac
void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
u32 mtk_r32(struct mtk_eth *eth, unsigned reg);