kernel: backport ethtool_puts

[openwrt/openwrt.git] / target / linux / generic / backport-5.15 / 733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch

diff --git a/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch b/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
index 066b70c5e2c3cc5478961422b8fec8ae6d4ba87b..b59638e772b80c3119a1973b96089150e19d4816 100644 (file)
--- a/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
+++ b/target/linux/generic/backport-5.15/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
@@ -1,3 +1,20 @@
+From f5d43ddd334b7c32fcaed9ba46afbd85cb467f1f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Sun, 19 Mar 2023 12:56:28 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for MT7981 SoC
+
+The MediaTek MT7981 SoC comes with two 1G/2.5G SGMII ports, just like
+MT7986.
+
+In addition MT7981 is equipped with a built-in 1000Base-T PHY which can
+be used with GMAC1.
+
+As many MT7981 boards make use of inverting SGMII signal polarity, add
+new device-tree attribute 'mediatek,pn_swap' to support them.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+
 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
 @@ -96,12 +96,20 @@ static int set_mux_gmac2_gmac0_to_gephy(
@@ -34,7 +51,7 @@
                mtk_eth_path_name(path), __func__, updated);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4755,6 +4755,26 @@ static const struct mtk_soc_data mt7629_
+@@ -4752,6 +4752,26 @@ static const struct mtk_soc_data mt7629_
        },
  };
  
@@ -61,7 +78,7 @@
  static const struct mtk_soc_data mt7986_data = {
        .reg_map = &mt7986_reg_map,
        .ana_rgc3 = 0x128,
-@@ -4797,6 +4817,7 @@ const struct of_device_id of_mtk_match[]
+@@ -4794,6 +4814,7 @@ const struct of_device_id of_mtk_match[]
        { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
        { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
        { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
@@ -128,7 +145,7 @@
  
  #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW         \
        BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
-@@ -963,6 +987,11 @@ enum mkt_eth_capabilities {
+@@ -957,6 +981,11 @@ enum mkt_eth_capabilities {
                      MTK_MUX_U3_GMAC2_TO_QPHY | \
                      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
  
@@ -140,7 +157,7 @@
  #define MT7986_CAPS  (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
                      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
                      MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
-@@ -1076,12 +1105,14 @@ struct mtk_soc_data {
+@@ -1070,12 +1099,14 @@ struct mtk_soc_data {
   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
   * @interface:         Currently configured interface mode
   * @pcs:               Phylink PCS structure