--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2791,9 +2791,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2952,9 +2952,6 @@ mt7531_mac_config(struct dsa_switch *ds,
case PHY_INTERFACE_MODE_NA:
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_2500BASEX:
return mt7531_sgmii_setup_mode_force(priv, port, interface);
default:
return -EINVAL;
-@@ -2869,13 +2866,6 @@ unsupported:
+@@ -3030,13 +3027,6 @@ unsupported:
return;
}
mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
mcr_new = mcr_cur;
mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
-@@ -3012,6 +3002,9 @@ static void mt753x_phylink_get_caps(stru
+@@ -3173,6 +3163,9 @@ static void mt753x_phylink_get_caps(stru
config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
MAC_10 | MAC_100 | MAC_1000FD;
/* This driver does not make use of the speed, duplex, pause or the
* advertisement in its mac_config, so it is safe to mark this driver
* as non-legacy.
-@@ -3077,6 +3070,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3238,6 +3231,7 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
state->link = !!(status & MT7531_SGMII_LINK_STATUS);
if (state->interface == PHY_INTERFACE_MODE_SGMII &&
(status & MT7531_SGMII_AN_ENABLE)) {
val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
-@@ -3107,16 +3101,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
+@@ -3268,16 +3262,44 @@ mt7531_sgmii_pcs_get_state_an(struct mt7
return 0;
}
}
static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-@@ -3157,6 +3179,8 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3318,6 +3340,8 @@ mt753x_setup(struct dsa_switch *ds)
priv->pcs[i].pcs.ops = priv->info->pcs_ops;
priv->pcs[i].priv = priv;
priv->pcs[i].port = i;
ret = priv->info->sw_setup(ds);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -400,6 +400,7 @@ enum mt7530_vlan_port_acc_frm {
+@@ -405,6 +405,7 @@ enum mt7530_vlan_port_acc_frm {
#define MT7531_SGMII_LINK_STATUS BIT(18)
#define MT7531_SGMII_AN_ENABLE BIT(12)
#define MT7531_SGMII_AN_RESTART BIT(9)