extern const struct ar8xxx_chip ar8327_chip;
extern const struct ar8xxx_chip ar8337_chip;
-#define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
+#define MIB_DESC_BASIC(_s , _o, _n) \
+ { \
+ .size = (_s), \
+ .offset = (_o), \
+ .name = (_n), \
+ .type = AR8XXX_MIB_BASIC, \
+ }
-#define MIB_DESC(_s , _o, _n) \
- { \
- .size = (_s), \
- .offset = (_o), \
- .name = (_n), \
+#define MIB_DESC_EXT(_s , _o, _n) \
+ { \
+ .size = (_s), \
+ .offset = (_o), \
+ .name = (_n), \
+ .type = AR8XXX_MIB_EXTENDED, \
}
static const struct ar8xxx_mib_desc ar8216_mibs[] = {
- MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
- MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
- MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
- MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
- MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
- MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
- MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
- MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
- MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
- MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
- MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
- MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
- MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
- MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
- MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
- MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
- MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
- MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
- MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
- MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
- MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
- MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
- MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
- MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
- MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
- MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
- MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
- MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
- MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
- MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
- MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
- MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
- MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
- MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
- MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
- MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
- MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXBROAD, "RxBroad"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, "RxPause"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXMULTI, "RxMulti"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXRUNT, "RxRunt"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
+ MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
+ MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
+ MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
+ MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
+ MIB_DESC_EXT(1, AR8216_STATS_FILTERED, "Filtered"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXBROAD, "TxBroad"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, "TxPause"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXMULTI, "TxMulti"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
+ MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
+ MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, "TxByte"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXDEFER, "TxDefer"),
+ MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
};
const struct ar8xxx_mib_desc ar8236_mibs[39] = {
- MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
- MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
- MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
- MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
- MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
- MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
- MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
- MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
- MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
- MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
- MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
- MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
- MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
- MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
- MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
- MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
- MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
- MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
- MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
- MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
- MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
- MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
- MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
- MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
- MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
- MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
- MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
- MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
- MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
- MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
- MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
- MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
- MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
- MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
- MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
- MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
- MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
- MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
- MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXBROAD, "RxBroad"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, "RxPause"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXMULTI, "RxMulti"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXRUNT, "RxRunt"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
+ MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
+ MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
+ MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
+ MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
+ MIB_DESC_EXT(1, AR8236_STATS_FILTERED, "Filtered"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXBROAD, "TxBroad"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, "TxPause"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXMULTI, "TxMulti"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
+ MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
+ MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, "TxByte"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXDEFER, "TxDefer"),
+ MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
};
static DEFINE_MUTEX(ar8xxx_dev_list_lock);
static LIST_HEAD(ar8xxx_dev_list);
+static void
+ar8xxx_mib_start(struct ar8xxx_priv *priv);
+static void
+ar8xxx_mib_stop(struct ar8xxx_priv *priv);
+
/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
static int
ar8xxx_phy_poll_reset(struct mii_bus *bus)
u64 t;
mib = &priv->chip->mib_decs[i];
+ if (mib->type > priv->mib_type)
+ continue;
t = ar8xxx_read(priv, base + mib->offset);
if (mib->size == 2) {
u64 hi;
}
static void
-ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
+__ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
+ bool ath_hdr_en)
{
u32 header;
u32 egress, ingress;
ingress = AR8216_IN_PORT_ONLY;
}
- if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
- header = AR8216_PORT_CTRL_HEADER;
- else
- header = 0;
+ header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
(pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
}
+static void
+ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
+{
+ return __ar8216_setup_port(priv, port, members,
+ chip_is_ar8216(priv) && priv->vlan &&
+ port == AR8216_PORT_CPU);
+}
+
static int
ar8216_hw_init(struct ar8xxx_priv *priv)
{
if (priv->initialized)
return 0;
+ ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
+ ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
+
ar8xxx_phy_init(priv);
priv->initialized = true;
return -EINVAL;
}
- if (priv->port4_phy)
+ if (priv->port4_phy) {
ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
AR8229_REG_OPER_MODE1_PHY4_MII_EN);
+ /* disable port5 to prevent mii conflict */
+ ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
+ }
ar8xxx_phy_init(priv);
__ar8216_init_port(priv, port, true, true);
}
+
+static int
+ar7240sw_hw_init(struct ar8xxx_priv *priv)
+{
+ if (priv->initialized)
+ return 0;
+
+ ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
+ ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
+
+ priv->port4_phy = 1;
+ /* disable port5 to prevent mii conflict */
+ ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
+
+ ar8xxx_phy_init(priv);
+
+ priv->initialized = true;
+ return 0;
+}
+
+static void
+ar7240sw_init_globals(struct ar8xxx_priv *priv)
+{
+
+ /* Enable CPU port, and disable mirror port */
+ ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
+ AR8216_GLOBAL_CPUPORT_EN |
+ (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
+
+ /* Setup TAG priority mapping */
+ ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
+
+ /* Enable ARP frame acknowledge, aging, MAC replacing */
+ ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
+ AR8216_ATU_CTRL_RESERVED |
+ 0x2b /* 5 min age time */ |
+ AR8216_ATU_CTRL_AGE_EN |
+ AR8216_ATU_CTRL_ARP_EN |
+ AR8216_ATU_CTRL_LEARN_CHANGE);
+
+ /* Enable Broadcast frames transmitted to the CPU */
+ ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
+ AR8236_FM_CPU_BROADCAST_EN);
+
+ /* setup MTU */
+ ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
+ AR8216_GCTRL_MTU,
+ AR8216_GCTRL_MTU);
+
+ /* setup Service TAG */
+ ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
+}
+
+static void
+ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
+{
+ return __ar8216_setup_port(priv, port, members, false);
+}
+
static void
ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
{
{
struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
- if (val->port_vlan >= AR8X16_MAX_VLANS)
+ if (val->port_vlan >= dev->vlans)
return -EINVAL;
priv->vlan_id[val->port_vlan] = val->value.i;
u8 ports;
int i;
- if (val->port_vlan >= AR8X16_MAX_VLANS)
+ if (val->port_vlan >= dev->vlans)
return -EINVAL;
ports = priv->vlan_table[val->port_vlan];
/* make sure that an untagged port does not
* appear in other vlans */
- for (j = 0; j < AR8X16_MAX_VLANS; j++) {
+ for (j = 0; j < dev->vlans; j++) {
if (j == val->port_vlan)
continue;
priv->vlan_table[j] &= ~(1 << p->id);
if (!priv->init) {
/* calculate the port destination masks and load vlans
* into the vlan translation unit */
- for (j = 0; j < AR8X16_MAX_VLANS; j++) {
+ for (j = 0; j < dev->vlans; j++) {
u8 vp = priv->vlan_table[j];
if (!vp)
memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
offsetof(struct ar8xxx_priv, vlan));
- for (i = 0; i < AR8X16_MAX_VLANS; i++)
+ for (i = 0; i < dev->vlans; i++)
priv->vlan_id[i] = i;
/* Configure all ports */
return ret;
}
+int
+ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+
+ ar8xxx_mib_stop(priv);
+ priv->mib_poll_interval = val->value.i;
+ ar8xxx_mib_start(priv);
+
+ return 0;
+}
+
+int
+ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+ val->value.i = priv->mib_poll_interval;
+ return 0;
+}
+
+int
+ar8xxx_sw_set_mib_type(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+ priv->mib_type = val->value.i;
+ return 0;
+}
+
+int
+ar8xxx_sw_get_mib_type(struct switch_dev *dev,
+ const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+
+ if (!ar8xxx_has_mib_counters(priv))
+ return -EOPNOTSUPP;
+ val->value.i = priv->mib_type;
+ return 0;
+}
+
int
ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
const struct switch_attr *attr,
int i, len = 0;
bool mib_stats_empty = true;
- if (!ar8xxx_has_mib_counters(priv))
+ if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
return -EOPNOTSUPP;
port = val->port_vlan;
mib_stats = &priv->mib_stats[port * chip->num_mibs];
for (i = 0; i < chip->num_mibs; i++) {
+ if (chip->mib_decs[i].type > priv->mib_type)
+ continue;
mib_name = chip->mib_decs[i].name;
mib_data = mib_stats[i];
len += snprintf(buf + len, sizeof(priv->buf) - len,
return ret;
}
+int
+ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
+ struct switch_port_stats *stats)
+{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ u64 *mib_stats;
+
+ if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
+ return -EOPNOTSUPP;
+
+ if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))
+ return -EOPNOTSUPP;
+
+ if (port >= dev->ports)
+ return -EINVAL;
+
+ mutex_lock(&priv->mib_lock);
+
+ mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
+
+ stats->tx_bytes = mib_stats[priv->chip->mib_txb_id];
+ stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];
+
+ mutex_unlock(&priv->mib_lock);
+ return 0;
+}
+
static int
ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
{
.description = "Reset all MIB counters",
.set = ar8xxx_sw_set_reset_mibs,
},
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "ar8xxx_mib_poll_interval",
+ .description = "MIB polling interval in msecs (0 to disable)",
+ .set = ar8xxx_sw_set_mib_poll_interval,
+ .get = ar8xxx_sw_get_mib_poll_interval
+ },
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "ar8xxx_mib_type",
+ .description = "MIB type (0=basic 1=extended)",
+ .set = ar8xxx_sw_set_mib_type,
+ .get = ar8xxx_sw_get_mib_type
+ },
{
.type = SWITCH_TYPE_INT,
.name = "enable_mirror_rx",
.apply_config = ar8xxx_sw_hw_apply,
.reset_switch = ar8xxx_sw_reset_switch,
.get_port_link = ar8xxx_sw_get_port_link,
-/* The following op is disabled as it hogs the CPU and degrades performance.
- An implementation has been attempted in 4d8a66d but reading MIB data is slow
- on ar8xxx switches.
-
- The high CPU load has been traced down to the ar8xxx_reg_wait() call in
- ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by
- the request to update the MIB counter is cleared. */
-#if 0
.get_port_stats = ar8xxx_sw_get_port_stats,
-#endif
+};
+
+static const struct ar8xxx_chip ar7240sw_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+ .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
+
+ .name = "Atheros AR724X/AR933X built-in",
+ .ports = AR7240SW_NUM_PORTS,
+ .vlans = AR8216_NUM_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar7240sw_hw_init,
+ .init_globals = ar7240sw_init_globals,
+ .init_port = ar8229_init_port,
+ .phy_read = ar8216_phy_read,
+ .phy_write = ar8216_phy_write,
+ .setup_port = ar7240sw_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .atu_flush_port = ar8216_atu_flush_port,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+ .get_arl_entry = ar8216_get_arl_entry,
+ .sw_hw_apply = ar8xxx_sw_hw_apply,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static const struct ar8xxx_chip ar8216_chip = {
.num_mibs = ARRAY_SIZE(ar8216_mibs),
.mib_decs = ar8216_mibs,
- .mib_func = AR8216_REG_MIB_FUNC
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8216_MIB_RXB_ID,
+ .mib_txb_id = AR8216_MIB_TXB_ID,
};
static const struct ar8xxx_chip ar8229_chip = {
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
- .mib_func = AR8216_REG_MIB_FUNC
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static const struct ar8xxx_chip ar8236_chip = {
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
- .mib_func = AR8216_REG_MIB_FUNC
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static const struct ar8xxx_chip ar8316_chip = {
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
- .mib_func = AR8216_REG_MIB_FUNC
+ .mib_func = AR8216_REG_MIB_FUNC,
+ .mib_rxb_id = AR8236_MIB_RXB_ID,
+ .mib_txb_id = AR8236_MIB_TXB_ID,
};
static int
ar8xxx_mib_work_func(struct work_struct *work)
{
struct ar8xxx_priv *priv;
- int err;
+ int err, i;
priv = container_of(work, struct ar8xxx_priv, mib_work.work);
err = ar8xxx_mib_capture(priv);
if (err)
- goto next_port;
+ goto next_attempt;
- ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
-
-next_port:
- priv->mib_next_port++;
- if (priv->mib_next_port >= priv->dev.ports)
- priv->mib_next_port = 0;
+ for (i = 0; i < priv->dev.ports; i++)
+ ar8xxx_mib_fetch_port_stat(priv, i, false);
+next_attempt:
mutex_unlock(&priv->mib_lock);
schedule_delayed_work(&priv->mib_work,
- msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
+ msecs_to_jiffies(priv->mib_poll_interval));
}
static int
static void
ar8xxx_mib_start(struct ar8xxx_priv *priv)
{
- if (!ar8xxx_has_mib_counters(priv))
+ if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
return;
schedule_delayed_work(&priv->mib_work,
- msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
+ msecs_to_jiffies(priv->mib_poll_interval));
}
static void
ar8xxx_mib_stop(struct ar8xxx_priv *priv)
{
- if (!ar8xxx_has_mib_counters(priv))
+ if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
return;
cancel_delayed_work_sync(&priv->mib_work);
struct switch_port_link link;
/* check for switch port link changes */
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0)
if (phydev->state == PHY_CHANGELINK)
+#endif
ar8xxx_check_link_states(priv);
if (phydev->mdio.addr != 0)
priv->mii_bus = phydev->mdio.bus;
priv->pdev = &phydev->mdio.dev;
+ ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
+ &priv->mib_poll_interval);
+ if (ret)
+ priv->mib_poll_interval = 0;
+
ret = ar8xxx_id_chip(priv);
if (ret)
goto free_priv;
priv->use_count++;
if (phydev->mdio.addr == 0) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
+ linkmode_zero(phydev->supported);
+ if (ar8xxx_has_gige(priv))
+ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
+ else
+ linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported);
+ linkmode_copy(phydev->advertising, phydev->supported);
+#else
if (ar8xxx_has_gige(priv)) {
phydev->supported = SUPPORTED_1000baseT_Full;
phydev->advertising = ADVERTISED_1000baseT_Full;
phydev->supported = SUPPORTED_100baseT_Full;
phydev->advertising = ADVERTISED_100baseT_Full;
}
+#endif
if (priv->chip->config_at_probe) {
priv->phy = phydev;
}
} else {
if (ar8xxx_has_gige(priv)) {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
+ linkmode_zero(phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
+ linkmode_copy(phydev->advertising, phydev->supported);
+#else
phydev->supported |= SUPPORTED_1000baseT_Full;
phydev->advertising |= ADVERTISED_1000baseT_Full;
+#endif
}
if (priv->chip->phy_rgmii_set)
priv->chip->phy_rgmii_set(priv, phydev);
static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
{
+ .compatible = "qca,ar7240sw",
+ .data = &ar7240sw_chip,
+ }, {
.compatible = "qca,ar8229",
.data = &ar8229_chip,
}, {
priv->pdev = &mdiodev->dev;
priv->chip = (const struct ar8xxx_chip *) match->data;
+ ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
+ &priv->mib_poll_interval);
+ if (ret)
+ priv->mib_poll_interval = 0;
+
ret = ar8xxx_read_id(priv);
if (ret)
goto free_priv;
swdev = &priv->dev;
swdev->alias = dev_name(&mdiodev->dev);
+
+ if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
+ priv->port4_phy = true;
+ swdev->ports--;
+ }
+
ret = register_switch(swdev, NULL);
if (ret)
goto free_priv;
projects / openwrt / staging / jogo.git / blobdiff